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Continues innovation and over-scaling will keep the current SoC's scaling near the historic Moore's Law trend. 3D-TSVs and inductive coupling as well as proper partitioning will allow the opportunity to beat Moore's Law in the next technology nodes.
An advanced Replacement Metal Gate (RMG) module was developed for 14nm node FinFETs and beyond. STI oxide extra recess increases on-current without any dedicated Source and Drain (SD) optimization. Tungsten (W) selective etch recesses work function metal (WFM), which reduces gate-contact capacitance, and improves AC performance and yields by increasing gate-contact space. Combination of work function...
Sub-40 nm Lgate asymmetric halo and source/drain extension transistors have been integrated into leading-edge 65 nm and 45 nm PD-SOI CMOS technologies. With optimization, the asymmetric NMOS and PMOS saturation drive currents improve up to 12% and 10%, respectively, resulting in performance at 1.0 V and 100 nA/mum IOFF of NIDSAT=1354 muA/mum and PIDSAT=857 muA/mum. Product-level implementation of...
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