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In this paper, the device performance in terms of its transport characteristics and reliability of the MOS devices on the SOI and strained-SOI have been examined. For the first time, both the transport and reliability characteristics have been established from experimental SOI and SSOI nMOSFETs. It was characterized by two parameters, the ballistic efficiency and the injection velocity. Experimental...
In this paper, we have proposed, fabricated and characterized a parallel electron beam micro-column with single-stranded carbon nanotube (CNT) filed emitters. The integrated micro-column consists of a self-aligned CNT field emitter array (FEA), and a multi-layered electrostatic Si focusing lens array. In our design, the emitters, gate and electrostatic lens array are electrically isolated, and each...
Well aligned CNTs on Ni/Ti/Si substrate were presented in this paper by the employment of pre-annealing process to the adhesive layer(Ti). SEM images show both the alignment and uniformity of the CNTs on pre-annealed substrates are better than that on non-treated substrate. The wall structures of the CNTs were also characterized and demonstrated different organizations. By this pre-annealing process,...
As device channel length continues to scale beyond 90nm, carrier transport in the ballistic regime becomes critically important. In this paper, the strain engineering and its correlation to the ION current enhancement of CMOS devices in the ballistic regime has been examined. It was characterized by two parameters, the ballistic transport efficiency and the injection velocity. Experimental verifications...
Device optimization on partially-depleted silicon-on-insulator (PD-SOI) CMOS is systematically performed in terms of circuit switching speed and power consumption. The effects of several key factors, such as threshold voltage (Vth), pre-amorphization implantation (PAI), and silicon film thickness (Tsi), are fully investigated and optimized to achieve optimal ring-oscillator performance. We found that...
SOI is today mainly used for high-speed CPU applications. The advantages brought by SOI are still questioned or not clearly understood and little information has been published about the comparison between bulk and SOI CMOS. First reason is that this comparison to be representative must be done for same process features such as gate length and gate oxide thickness, second reason is that designing...
High performance SiGe channel CMOS on (100) and (110) Si surfaces with process-induced strained-Si technologies was fabricated and compared to Si channel devices. The mechanism of stress-induced performance enhancements in SiGe channel devices on both (100) and (110) surfaces was systematically investigated. Device-level piezoresistance coefficients for Si and SiGe channels were extracted from CMOS...
Mobility and strain mechanisms of SiGe channel pMOSFETs fabricated with <110> channel direction on (110) Si substrate (<110>/(110) SiGe channel) have been studied in details for the first time. The combination of substrate orientation, high mobility channel material and extrinsic stained-Si process demonstrates the ultra high mobility enhancement and results in 80% current gain. The piezoresistance...
A unique ultra shallow junction scheme featured with integrating diffusion barrier into eSiGe:B strained pMOSFETs has been demonstrated. Embedded diffusion barrier (EDB) drastically suppresses boron out-diffusion from subsequent thermal treatment, thus resulting in superior short channel control. This approach enables the formation of ultra shallow junction, over 30% junction depth reduction, while...
The promising potential of (110) SiGe channel as next generation high performance p-MOSFETs is well demonstrated in this work. As high as 48% of drive current enhancement on SiGe channel p-MOSFETs fabricated on (110) surface have been achieved for the first time. In addition, combining with compressive stress capping layer, the (110) SiGe channel p-MOSFETs exhibits an extended 81% Idsat gain with...
For the first time, 75% and 7% drive current improvement is simultaneously achieved in both N/PMOS by adopting ultimate spacer process (USP) with a single stress liner. High out-of-plane stress in the channel accounts for the simultaneously enhanced drive current in N/PMOS. A 15% speed enhancement without compromising yield and product qualification in field-programmable gate arrays (FPGA) confirms...
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