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We report on the experimental demonstration of a novel n-channel GaN epilayer RESURF GaN MOSFET with good trade-off between breakdown voltage and specific on-resistance for the first time. Device with 4 mum channel length and 16 mum RESURF length has breakdown voltage up to 730 V with specific on-resistance 34 mOmega-cm2 (VG-VT=20 V).
We report on the demonstration of enhancement-mode n-channel GaN-based hybrid MOS-HFETs realized on AlGaN/GaN heterostructure on silicon substrates with a large drain current operation. The GaN-based hybrid MOS HFETs realized the threshold voltage of 2.8 V, the maximum drain current of over 70 A with the channel width of 340 mm. This is the best value for an enhancement-mode GaN-based FET. The specific...
We have studied and optimized the breakdown voltage of enhancement-mode n-channel GaN hybrid MOS-HEMTs on sapphire substrate. These MOS-gated transistors, with different Mg doped p-type GaN layer underneath the unintentional doped AlGaN/GaN layer, have breakdown voltage as high as 1300 V using a dielectric isolation (DI) RESURF approach.
We report on the experimental demonstration of a novel n-channel GaN epilayer RESURF GaN MOSFET with good tradeoff between breakdown voltage and specific on-resistance for the first time. Device with 4-mum channel length and 16-mum RESURF length has breakdown voltage up to 730 V with specific on-resistance 34 mOmegamiddotcm2 (VG - VT = 20 V), best reported to date.
We report on the demonstration of enhancement- mode n-channel lateral implanted GaN high-voltage MOSFET with breakdown voltage up to 2.5 kV or specific on-resistance as low as 30 mOmegaldrcm2. With proper RESURF dose, drain current up to 0.1 A and breakdown voltage up to 1570 V is realized on the same device. The reliability lifetime defined by the failure criteria of DeltaIp/Ip=20% was determined...
An 80 V class integrable lateral trench power MOSFET based on a shallow trench (~1.0 mum) structure with a low Figure of Merit (RontimesQg) for high frequency switching applications is presented. A simulated optimized MOSFET exhibits a Figure of Merit of 240 mOhm-nC, which is over 2.5X improvement on the best reported lateral trench power MOSFETs in the same voltage class. Prototype devices from the...
The authors discuss the impact of device cell geometry on the safe operating area (SOA) of IGBTs (insulated-gate bipolar transistors). Two-dimensional computer simulations of the electric field distribution and avalanche breakdown have been performed for a variety of cell geometries. Simulation of the square-cell and linear-cell geometries used in previous devices showed that the SOA is determined...
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