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This work proposes a secure Network-on-Chip (NoC) approach, which enforces the encapsulation of sensitive traffic inside the asymmetrical security zones while using minimal and non-minimal paths. The NoC routing guarantees that the sensitive traffic communicates only through trusted nodes, which belong to a security zone. As the shape of the zones may change during operation, the sensitive traffic...
This paper presents a complexity analysis of 3D High Efficiency Video Coding (3D-HEVC) depth maps intra prediction. The 3D-HEVC inserts new coding tools in depth maps intra prediction such as Depth Intra Skip (DIS), Depth Modeling Modes (DMMs) and Segment-wise DC (SDC). Therefore, it is important to understand the complexity of each module to allow the design of new complexity reduction techniques...
This paper evaluates emerging TSV-interconnected memory technologies employed as the main memory of 3D Symmetric MultiProcessing (SMP). As the target architecture, we implemented a typical 3D SMP including L1 and L2 caches together with some tiers of main memory. Besides, we employed DDR3 as a baseline comparison to normalize all results. The experimental results show a tradeoff between energy efficiency...
Malicious applications target Multi-Processors System-on-Chip (MPSoCs) to capture sensitive information or disrupt normal operation; therefore, security is now a design requirement for MPSoC design. Network-on-Chip (NoC) is a key communication structure to aid in the overall MPSoC protection. Firewall-based NoC protection allows data exchange monitoring and controlling according to the MPSoC security...
The Last-Level Cache (LLC) influences the overall system performance and power dissipation in multicore systems significantly. This paper evaluates five LLC architectures targeting execution time, dynamic and static power dissipation, and area consumption. They are measured using the widely adopted PARSEC benchmark suite for parallel shared-memory systems. Employing Gem5 full-system simulator and...
Multi-Processors Systems-on-Chip (MPSoCs), as a key technology enabler of the new computation paradigm Internet-of-Things (IoT), are currently exposed to attacks. Malicious applications can be downloaded at runtime to the MPSoC, infecting IP-blocks connected to a Network-on-Chip (NoC) and opening doors to perform Timing Side Channel Attacks (TSCA). By monitoring the NoC traffic, an attacker is able...
Newest technologies of integrated circuits fabrication allow billions of transistors arranged in a single chip enabling to implement a complex parallel system, which requires a high scalable and parallel communication architecture, such as a Network-on-Chip (NoC). These technologies are very close to physical limitations increasing faults in manufacture and at runtime. Thus, it is essential to provide...
Following the current trend in the semiconductor industry (MPSoC) and the massive advances presented by all things interconnected (Internet of Things), a massive quantity of private and metadata is being transferred through insecure channels. In the industry, almost no attention is given to the amount of data that can be collected from different individuals, just by getting access to their house appliances...
Multiprocessor System-on-Chip (MPSoC) based on Network-on-Chip (NoC) integrates a large amount of Processor Elements (PEs) to fulfill the performance requirements of several applications. These applications are composed of a set of intercommunicating tasks, which are dynamically mapped onto PEs of the target architecture. However, the efficient task-mapping requires some previous steps, among them...
The overall system-on-chip performance depends on the network architecture, whose communication latency significantly impacts on the application performance. The challenge for on-chip networks is reducing costs while providing high performance such as low latency and high throughput. One alternative to achieve such goals is to implement efficient router architectures capable of fast packet switching...
This paper discusses the impact of routing arbitration mechanism on the packet latency for 3D NoC (Three-dimensional Network-on-Chip) architectures. We implemented several variations of Round-Robin mechanisms to explore how the arbitration efficiency affects the packet latency. The underlying objective is to discuss the compromise of increase router area and energy consumption through investing on...
This paper presents Tiny NoC, which is a scalable and efficient 3D mesh architecture developed to minimize latency and NoC area. First, we show a theoretical analysis of latency and area occupancy to demonstrate Tiny NoC efficiency when compared to a basic mesh NoC. Then, we select a set of synthetic and mapping independent traffic with several injection rates to analyze the advantages and weaknesses...
The emergence of wireless networks has contributed to a growing number of studies and protocols regarding its performance and reliability requirements, among others. Several issues have to be considered when deploying such devices under harsh environmental conditions. These issues often force the designer to adopt decisions that are usually difficult to verify in real world settings. In order to mitigate...
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