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Through silicon vias (TSVs) are regarded as one of the key enabling component to achieve three-dimensional (3D) integrated circuit (IC) functionality. In this paper, we present the investigation on TSV protrusion and stress at different annealing conditions tested by means of optical profiler and high efficiency micro-Raman microscopy. Finite element method is utilized to model and simulate the thermo-mechanical...
Thermal stress is induced by high temperature manufacturing processes, due to the mismatch of Coefficient of Thermal Expansion s (CTE) between silicon, dielectric material and copper. In this paper, thermal stress around Through-Silicon-Vias (TSVs) was discussed using 3D FEA transient method. Stress distributions near a TSV and TSVs array were investigated after dielectric liner deposition, barrier...
Flip-chip ball grid array (FCBGA) packaging was developed to meet the requirements of high I/O density and high electrical performance and the trend of persistent miniaturization of electronic products. Underfill is usually used in flip-chip packaging to fill the gap between the silicon die and the substrate to provide solder bumps protection, compensation of the coefficient of thermal expansion (CTE)...
Through silicon vias (TSVs) have been extensively studied because it is a key enabling technology for achieving three dimensional (3D) chip stacking and silicon interposer interconnection. The large mismatch between the coefficients of thermal expansion (CTE) of copper and silicon induces stress which is critical for the TSV reliability performance. This paper proposes analytical solutions of stress...
3D integration using TSVs is a promising method to achieve further improvements for future electronic systems. When Copper TSVs are fabricated, Stress is induced in silicon near the TSV by CTE mismatch between filling copper and silicon substrate. For the substrate which has active circuits, the induced stress will influence the performance of the devices fabricated therein. To understand the impact...
With the trend of commercialization of through-silicon vias (TSVs) in 3D integrated microsystems, new TSVs filling processes are developed to meet the requirement of low-cost fabricating of high-electrical performance and high-thermal reliability TSVs without any voids. In this paper, Sn-based IMCs are used as the filling materials for the formation of conductive path of TSVs. The Sn-based IMCs filling...
Through silicon vias (TSVs) attract considerable amount of attention and activity in recent years as a main means to achieve three-dimensional (3D) integrated circuit (IC) functionality. However, the new technology poses new integration challenges as well as new testing and verification challenges. This paper presents the latest progress in TSV non-destructive testing by means of X-ray microscopy,...
Due to the differences in the thermal expansion coefficients of copper and silicon, a large thermal stress develops at the interface between a Cu-filled via and both the insulation layer and the surrounding silicon when the structure is subjected to temperature loading. In this paper four TSV geometries are considered in an effort to investigate the role of via geometry on stress relief. Thermo-mechanical...
The coefficient of thermal expansion (CTE) of metal (e.g., copper, tungsten and solder) filled in through silicon via (TSV) is a few times higher than that of silicon. Thus, when the metal filled TSV is subjected to temperature loadings, there is a very large local thermal expansion mismatch between the metal and the silicon/dielectric (e.g., Si02), which will create very large stresses at the interfaces...
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