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We have proposed inhibition mechanism of common Al-capping technique for pMOSFET threshold-voltage (Vth) control for the first time, and have established effective Ti-capping technique using metal gate and Hf-based high-k dielectrics. Ti-capping technique can adjust lower Vth than Al-capping one due to the suppression of counter dipole and solid solubility limit in doping. Moreover, Ti-capping technique...
This paper reviews main technologies of embedded silicon germanium (eSiGe) for 45 nm node and beyond .There are three key techniques and an item to be considered carefully as follows. The first technique is a low temperature of epitaxial growth at 550degC to suppress stacking faults in eSiGe layer. The second one is a controlling of recess shape for eSiGe. Sigma(Sigma)-shaped recess is applied, because...
A new powerful strain booster named as dopant confinement layer (DCL) technique is proposed for the first time. DCL technique is a novel stress memorization technique (SMT). Our proposed method doesn't require any additional capping layers used in SMT. DCL fabricated directly on the gate dielectric film effectively improved drive currents without degrading short channel immunity because DCL technique...
The impact of defects on the short channel effects (SCE) and the drivability of a pMOSFET with a SiGe source/drain is described, and useful methods to reduce defect formation are suggested. The influence of defects on device performance is found to become more severe as recess depth increases and/or channel length decreases. By optimizing the epitaxial process, including an in-situ precleaning step,...
High-performance low operation power (LOP) transistors were developed for 45nm node universal applications. A high uniaxial strain and low resistance NiSi technique, enhanced by a slit under the slim and high Young's modulus (YM) offset spacer covered with dual stress liner (DSL), were used for electron and hole mobility enhancement and parasitic resistance (Rsd) reduction. The junction profile was...
Aggressively scaled 30nm gate CMOSFETs for 45nm node is reported. We successfully improved a higher drive current with keeping the short channel effect by Sigma shaped SiGe-source/drain (Sigma SiGe) structure using compressive-stressed liner. In addition, we developed novel stack-SIN gate dielectrics by using bis-tertiarybutylamino-silane (BTBAS)/NH3. Novel stack-SIN gate dielectrics show higher immunity...
Aggressively scaled 30 nm gate CMOSFETs for 45 nm node is reported. We successfully improved the short channel effect with keeping a high drive current by Sigma shaped SiGe-source/drain (SiGe-SD) structure. Both hole mobility and source/drain extension (SDE) resistance in pMOSFET are improved by combination of optimized Sigma shaped SiGe-SD and slit-embedded B-doped SiGe-SDE. Electron and hole mobility...
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