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We investigated the impact of oxide liner elastic modulus and thickness on through-silicon via (TSV) Cu pumping and stress. A low-k dielectric liner showed a decrease in residual Cu pumping and TSV stress compared to O3-TEOS SiO2 and ALD SiO2 liners. For TSVs with a post-plating anneal, residual Cu pumping decreases from (102 ± 7) nm to (11 ± 1) nm (99.9th percentile) when the O3-TEOS SiO2 liner thickness...
An analytical model simulating the bowing at wafer or thin die level was applied to imec's 3D interposer technology. The calibration methodology is explained. A good correlation between simulation and measurement has been found at different stages during the processing. Secondly, a model combining all the interposer features was used to simulate the bowing induced at wafer and thin die level. Finally,...
During a solder reflow process, IC components deform under a rather excessive temperature loading. A too high warpage at temperatures above solder melting, can cause either that the joints in the corner are not soldered to the PCB pads, or that the solder joints are shorted due to compressing of the corner joints. In this work, the warpage of a 35by35 mm2 large PBGA package has been measured during...
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