The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper presents a 5–50 Gb/s quarter-rate transmitter with a 4-tap feed-forward equalization (FFE) based on multiple-multiplexer (MUX). A bandwidth enhanced 4∶1 MUX with the capability of eliminating charge-sharing effect is proposed to increase the maximum operating speed. To produce the quarter-rate parallel data streams with appropriate delays, a compact latch array associated with an interleaved-retiming...
In this paper, a dual-channel 12-Bit 800MS/S time-interleaving pipeline ADC is presented. Each pipeline channels share a common sample-and-hold amplifier either to eliminate the timing mismatch or to diminish the residue charge. Multiple voltage supply is utilized, which makes using wideband single stage cascoded OTA possible. An on-chip input buffer is applied to reduce the kick-back noise from the...
A novel aperture error reduction technique for subrange successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. By reusing capacitors of flash ADC during fine conversion phase, thermometer coarse capacitors belonging to CDAC can be removed from the circuit. Compared with the conventional subrange SAR ADC without front-end T/H, this technique can minimize...
This paper presents a 40Gbps SerDes transceiver consuming only 190mW power. The transmitter employs serializing time window search technique and 2-tap pre-emphasis. The receiver implements power-efficient front-end circuits including current-integrating FFE and cascaded dynamic comparators. The CDR employs a bang-bang phase detector, and the integral path and proportional path are separated. Fabricated...
This paper describes design techniques of enabling energy-efficient 3-tap decision feedback equalizer (DFE) to operate adaptively at 40Gb/s in 65nm CMOS technology. First, we propose a closed-loop architecture utilizing three techniques to achieve the 1st tap stage design, namely a merged latch and summer, reduced latch gain, and a dynamic latch design. Then, we suggest to merge the feedback MUX with...
This paper presents a 40 Gb/s (38.4-to-46.4 Gb/s) half rate SerDes transmitter with automatic serializing time window search and 2-tap pre-emphasis. By implementing a serializing time window search loop, the serializing timing is guaranteed and circuits running at the highest speed such as latches for retiming and clock tree buffers for delay matching are eliminated. A divider-less sub-harmonically...
This paper presents a 50Gbps half rate SerDes transmitter with automatic serializing time window search. By implementing a serializing time window search loop, the serializing timing is guaranteed and circuits running at highest speed such as latches for retiming and clock tree buffers for delay matching are eliminated. Fabricated in 65nm CMOS technology, the transmitter running at 50Gbps consumes...
A low-cost low-power baseband processor for passive UHF RFID Tag based on EPC C1G2 protocol is presented in this paper. In order to minimize the power consumption, a novel digital baseband architecture is proposed and a series of low-power design approaches are adopted, including asynchronous design, clock-gating, low operating frequency, reuse of registers, etc. The baseband processor supports eleven...
This paper presents a 10-bit 400 MS/s CMOS current-steering digital-to-analog converter (DAC) for video applications. The proposed DAC adapts segmented architecture, composed of 6 MSBs unary and 4 LSBs binary-weighted cells. An improved current switching scheme is developed to compensate the systematic error further. The post-layout simulation results show that the converter achieves a spurious-free...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.