The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A simulation study of lithography induced layout variations in 6-T SRAM cells is presented. Lithography simulations of a complete 6-T SRAM cell layout, including active n+/p+ regions layer and poly-gate layer were performed. The smallest feature size was assumed to be 45 nm. 76 positions of the projector focus were simulated for each layer in total. TCAD simulations of 32nm single gate FD SOI MOSFETs...
The simulation of process options for advanced CMOS devices is discussed in this work. Advanced rapid thermal annealing schemes are applied to fully depleted silicon on insulator MOSFETs with a physical gate length of 22 nm. Process induced mechanical stress is simulated for PMOS transistors to improve the Ion-Ioff relation. A modification of the linear piezo model is presented to simulate the hole...
In this paper, a TCAD-based simulation study on lithography process-induced gate length variations has been performed. This study aims at evaluating fully depleted silicon on insulator (FD SOI) MOSFETs for next generation CMOS devices. Critical dimensions (CDs) have been obtained using rigorous lithography simulations. The impact of the resulting gate length variations on the electrical behavior of...
In this work, the influences of advanced annealing schemes, spike and flash annealing and combinations of them, on the electrical behavior of modern FD SOI MOSFETs have been investigated by numerical simulations. Process simulations have been performed for comparing the two-dimensional diffusion behavior of the dopants under the different annealing schemes. Device simulations have been performed for...
Problems of pre-silicon compact modeling of nano-scaled silicon-on-insulator MOSFETs are addressed using the extraction of SPICE model parameters directly from numerical TCAD simulations. Although there are difficulties in the parameter extraction for the standard SPICE compact models we show by a direct comparison with the results of the numerical mixed-mode TCAD simulations that with some trade-offs...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.