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A 0.13 mum CMOS Cartesian loop transmitter IC with calibration and loop setting scheme of less than 5 mus is fabricated in order to keep high efficiency in wide output power range. The proposed scheme adjusts amplitude, phase, loop gain by using TX modulated signal for fast loop setting. Adjacent channel power leakage ratio (ACPR) is improved by 18 dB. The transmitter IC without PA consumes 62 mA,...
In this paper, a single-chip dual-mode 8-band 130 nm CMOS transceiver including A/D/A converters and digital filters with 312 MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (high speed uplink packet access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and...
A 0.13um CMOS pre-power amplifier with 90dB gain range is fabricated. The pre-power amplifier consists of 4 variable attenuators and 3 fixed gain amplifiers, where the proposed attenuator suppresses the attenuation variation due to Vth variation. The pre-power amplifier outputs +4dBm with 75mW and -80dBm with 65mW. The ACPR is -48dBc and the EVM is less than 1.0% at Pout = +4dBm. The attenuation variation...
A time-to-digital converter (TDC) utilizing a vernier delay line (VDL) technique has relatively large timing errors when the mismatch of the vernier delay is large. In order to overcome this problem, we propose a technique for compensating the vernier delay mismatch using multiple ring oscillation measurements of VDL. We verified it using an on-die jitter measurement circuit implemented in 90 nm CMOS...
A 5 GHz MIMO direct-conversion transceiver composed of 2 transmitters (TXs) and 3 receivers (RXs) is fabricated with 0.13 mum CMOS technology. Die size is 4.56 mm times 7.7 mm. For driving 10 GHz LO signal lines of 5 mm length for both TXs and RXs, inductor-less low-power LO repeaters are equipped in individual LO paths. A linearized RF variable gain amplifier is proposed for low power operation....
An energy-saving system for SOCs using multiple threshold voltage CMOS was developed. It uses process sensors and process-voltage conversion tables generated from static timing analysis results to adjust the supply' voltage according to die-to-die process variation. We applied this system to an embedded dual-core microprocessor using 90 nm triple threshold voltage CMOS technology. When the microprocessor...
A real-time on-die noise sensor continuously detects up to 100 noise events per second without disturbing processor operations, using a 400kb/s serial interface. The noise sensor uses histogram counters and variable detection windows. The sensor measures periodic and single-events in real time. The noise sensor is implemented in a 90nm CMOS testchip.
An energy-saving system for SOCs using multiple threshold voltage CMOS was developed. It equips process sensors and process-voltage conversion table generated from static timing analysis results, and adjusts. The supply voltage according to die-to-die process variation. We applied this system to an embedded dual-core microprocessor using 90nm triple Threshold voltage CMOS technology. When the microprocessor...
This paper proposes a new plasma damage model that can explain and estimate the plasma damage in a CMOS LSI by taking into account the additional factor of pattern density. Reliability data presented in this paper shows that plasma damage to MOSFET gate oxide in a CMOS LSI cannot be fully explained by considering only antenna and aspect ratio theory. To verify the model on a CMOS LSI, a test pattern...
A 25- mu m/sup 2/ poly-Si PMOS load SRAM (static random access memory) cell, called a PPL cell, has been developed. The cell has been excellent retention characteristics, high soft-error immunity, and low standby power. These advantages are achieved using poly-Si PMOS loads and cross-coupled stacked capacitors formed between the NMOS and the stacked poly-Si PMOS. A large poly-Si PMOS ON current lowers...
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