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A 64-Gb/s high-sensitivity non-return to zero receiver (RX) data-path is demonstrated in the 14-nm-bulk FinFET CMOS technology. To achieve high sensitivity, the RX incorporates a transimpedance amplifier whose gain and bandwidth are co-optimized with a 1-tap decision feedback equalization (DFE). The DFE, which operates at quarter-rate, features a look-ahead speculation to relax DFE timing to 4 unit-interval...
A 12 b 600 MS/s 2 × TI SAR ADC achieving 60 dB SNDR at Nyquist is presented. Time-interleaving errors are calibrated in the background by using a linear but noisy reference ADC. A test chip demonstrates that interleaving spurs are reduced to below −70 dBFS using an off-chip least-mean-squares (LMS) algorithm. The reference ADC is an 8 b SAR with reduced sampling capacitance and input amplitude. This...
A DDR4 transmitter (TX) for direct-attach memory on a processor chip is presented as well as the design of the associated low-dropout linear voltage regulators (LDO) that generate the split-mode supply voltages for the thin-oxide protection of the TX output stages operated from the 1.2 V DDR4-supply. The TX uses AC-boost equalization. Signal-integrity (SI) simulations have shown that pre-emphasis...
We report a 5Gb/s data link implemented in 14nm FinFET CMOS SOI technology in which a single transmitter (TX) broadcasts NRZ data to eight receivers (RXs) distributed along an on-chip RC-dominated 10mm-long channel. The TX comprises a full-rate AC-coupled 2-tap FIR driver with a quarter-rate pre-driver. Each RX is equipped with a novel decision-gated 1-tap speculative DFE optimized for low-power....
A 300MS/s 12b SAR ADC achieving 61.6dB peak SNDR is presented. It reaches 60.5dB SNDR and 78.7dB SFDR with 0.8Vpp,diff input amplitude at Nyquist. The key elements are a comparator with inverter-based preamplifier and a SAR-based common-mode regulation. The regulation adjusts the common mode on a sample-by-sample basis to improve common-mode rejection. The ADC consumes 7.0mW from a single 0.85V supply,...
This work presents an 850nm VCSEL-based multi-mode 32Gb/s NRZ optical link with circuits in 14nm bulk FinFET CMOS. The TX uses a 3-tap, 1\2-Ul-spaced FFE to improve eye opening. The RX uses a low-BW, low-noise TIA and a speculative 1-tap DFE for high sensitivity. The TX and RX power efficiencies are 3.3 and 1.4pJ/bit, respectively. The link sensitivity is −11.7dBm OMA at BER=10"12 with PRBS31...
High-speed SAR ADCs became popular with modern CMOS technologies because of their mostly digital logic, making them highly suitable for compact and power-efficient multi-GS/s time-interleaved ADCs. As many applications cannot tolerate input swings ≥1Vppd, comparator noise limits the SNDR of SAR ADCs, making gain stages necessary for higher SNDR - either as comparator pre-amplifiers or between pipelined...
The rapid increase of bandwidth requirements between processors in high-end servers motivates the integration of optical interconnects on the first-level processor package [1]. In this perspective, additional bandwidth density can be achieved by integrating optical transceivers directly into the processor die. Optically enabled CPUs can provide energy-efficient, low-latency interconnects over long...
The constantly increasing need for I/O bandwidth push electrical backplane links to data rates of 50Gb/s and above. Although board materials have improved significantly, backplane links are increasingly limited by signal attenuation while suffering from ISI, jitter, device noise and cross-talk. In this paper we summarize these limitations, and show possible directions to cope with them in order to...
A 50V input range, common-mode and differential, 14bit 2-step SAR ADC is presented. The ADC operating at 250kS/s for a 50VPP input signal on a 15V common-mode voltage achieves 97,8dB SFDR and 80:2dB SNR, while consuming 4.29mW from a single 3.3V supply. The 2-step architecture accomplishes an increase in resolution by reusing conversion residue, with a time-shared configurable amplifier/comparator...
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