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For high side gate driver IC, we applied to single p-type isolation technic between high side region and 700V LDMOS (lateral double-diffused MOS) drain to reduce electric potential of junction termination by the crossing drain metal of 700V LDMOS. This single p-type isolation has low doping concentration to be fully depleted for maintaining a high voltage, normally more than 700V. It is limited to...
The MOSFET flicker (1/f) noise is reduced by 1 to 2 orders by incorporating fluorine into the oxide-silicon interface. This is attributed to a reduction in interface state density with fluorine as confirmed by charge pumping measurements. Random-Telegraph Signal (RTS) noise measurements on small-size MOSFETs show a considerable increase in the on-off time-constants with fluorine. High-resolution TEM...
The MOSFET flicker (1/f) noise is reduced by 1 to 2 orders by incorporating fluorine into the oxide-silicon interface. This is attributed to a reduction in interface state density with fluorine as confirmed by charge pumping measurements. Random-Telegraph Signal (RTS) noise measurements on small-size MOSFETs show a considerable increase in the on-off time-constants with fluorine. High-resolution TEM...
The MOSFET flicker (1/f) noise is reduced by 1 to 2 orders by incorporating fluorine into the oxide-silicon interface. This is attributed to a reduction in interface state density with fluorine as confirmed by charge pumping measurements. Random-Telegraph Signal (RTS) noise measurements on small-size MOSFETs show a considerable increase in the on-off time-constants with fluorine. Highresolution TEM...
In BCD process for high voltage Smart Power IC, junction breakdown instability in DTI(Deep Trench Isolation) process is strongly depend on the process-induced mechanical stress and DTI test pattern shape. The DTI test pattern with sharp corner generates larger charge trap density and larger breakdown voltage shift than that of round corner test pattern. Through 3D TCAD simulation and SEM/TEM analysis,...
a 12V low Vgs (1.8V) RF-N/PLDMOS have been successfully implemented on the 0.18 µm analog CMOS process without thermal budget addition. N- and P-ch LDMOS needs additional body and drift implants, respectively. A short channel length and a small overlap of gate-to-drain were accomplished by the optimization of implant conditions for the source halo and the drift region which is followed by the gate...
Flicker (1/f) noise and TCR are compared for arsenic- and phosphorus-doped polysilicon in a 0.18 μm CMOS base technology. Resistors implanted with arsenic exhibit about 4 times higher noise than with phosphorus at the same dose and thermal budget. The TCR of arsenic-doped polysilicon is negative, near −1065 ppm/K, while that of phosphorus-doped resistors positive, about + 590 ppm/K. The mismatch of...
A versatile 30V analog CMOS process in a 0.18 μm technology node has been developed by using cost-effective and modular fashion. To reduce the thermal budget deep NWELL isolation is formed after CMOS well formation. The drain-extended (DE) CMOS from 7V to 30V shows very competitive trade-off performance between the breakdown voltage and the specific on-resistance. In addition, low 1/f noise of 5V...
In this paper, we present a new isolated Low Vgs NLDMOS in 0.35um BCDMOS process. The proposed LDMOS is fully isolated from substrate and has very lower Rsp(specific on-resistance) than other competitors. This device can apply a negative bias to drain and it can be used in AMOLED application. The proposed LDMOS devices in 30–40V ranges have the lowest Rsp with other competitors in 0.13–0.35um BCDMOS...
This paper reviews the technology trends of BCD (Bipolar-CMOS-DMOS) technology in terms of voltage capability, switching speed of power transistor, and high integration of logic CMOS for SoC (System-on-Chip) solution requiring high-voltage devices. Recent trends such like modularity of the process, power metal routing, and high-density NVM (Non-Volatile Memory) are also discussed.
0.18μm BCD technology with the best-in-class nLDMOS is presented. The drift of nLDMOS is optimized to ensure lowest Rsp by using multi-implants and appropriate thermal recipe. The optimized 24V nLDMOS has BVDSS=36V and Rsp=14.5 mΩ-mm2. Electrical SOA and long-term hot electron (HE) SOA are also evaluated. The maximum operating voltage less than 10% degradation of on-resistance is 24.4V.
We present a new 0.35um BCDMOS technology with a capability of 8 to 60V NLDMOS. The proposed process do not need level shifter, charge pump and boost up due to the same gate oxide thickness with logic 5V CMOS. And the Rsp of the proposed 24V NLDMOS structure is lower by 46% than conventional structure. The process has no thermal budget modification but use simple additional implant step. Also it is...
We present a new 0.3 5um BCD technology with a capability of 8 to 60V p-ch LDMOS. The proposed p-ch LDMOS employs the S-PWELL in the p-epi region to ensure high breakdown voltage and low on-resistance. The Rsp of the proposed 60V p-ch LDMOS is lower by 42% than conventional one. And we modified the 300Å gate oxide of the original p-ch LDMOS to 125Å so that the proposed p-ch LDMOS is efficient for...
We experimentally demonstrate a super-junction LDMOS transistor in a 0.18 mum BCD technology. The buffered super-junction structure is implemented by the use of existing N- and P-drift layer, which are optimized for conventional 20 V to 30 V LDMOS transistors. The breakdown voltage and the specific on-resistance of the fabricated super-junction LDMOS are 98.6 V and 1.01 mOmegaldrcm2, respectively...
We present a new BCD technology in a 0.18 μm technology platforms with a capability of 7 to 60V high-voltage devices such as DEMOS and LDMOS. The developed 0.18 mum BCD process provides various kinds of high voltage LDMOS such as 7, 12, 20, 50, 60 V LDMOS transistors for variety of applications. The power LDMOS transistors in the process have very competitive specific on-resistance compared to previous...
This paper report 85 V high-side LDMOS which is implemented in a conventional 0.3 5 um BCDMOS process using one additional mask. The process has no thermal budget modification but use simple additional implant step. Also it is completely compatible with the conventional BCDMOS process and has similar performances with 80 V SOI LDMOS.
We propose a new self-aligned ITLDD process with minimum gate-drain overlap capacitance by employing a double stepped gate oxide under the overlapped gate and present our device and circuit simulation results to confirm the merits of the proposed gate-drain overlapped structures with respect to reliability and device performance by employing 2-D and 3-D device simulators.
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