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The ruggedness of SiC pn diode was investigated. The SiC pn diode was confirmed to operate at over 800°C, a higher temperature than Si device's destruction temperature, and to endure a large current of over 1000A (2000A/cm2) per one chip. The resistance of the diode showed a positive temperature coefficient until its destruction. This was different from the destruction of Si pn diodes.
The ruggedness of SiCGT (SiC Commutated Gate Turn-off Thyristor) was investigated. The SiCGT was confirmed to operate at over 1200°C, a higher temperature than Si device's destruction temperature. The SiCGT endured a large current of over 2000A (2470A/cm2) per one chip. Positive temperature coefficient resistor behavior could be found during the destruction of SiCGT, which was different from the destruction...
A method of integrating high performance and low-cost Cu ultra low-k (ULK) SiOC(k=2.0) hybrid interconnects with SiOC(k=2.65) hard mask structure has been developed. The method combines Cu/ULK interconnects with the self-formed MnOx barrier layer that was shown to have lower resistance and higher reliability than Cu alloys. Moreover, dual-damascene (DD) interconnects with MnOx barrier layer showed...
Lithium doped K0.5Na0.5NbO3 films were fabricated by chemical solution deposition on Pt/TiO2/SiO2/Si substrates. Homogeneous and stable precursor solutions were prepared by controlling the reaction of starting metal alkoxides. Perovskite KNN single phase thin films were successfully synthesized on Pt/TiOx/SiO2/Si substrates. The 1.2 mum-thick KLNN film annealed at 650degC exhibited a ferroelectric...
We have developed novel SIC devices, both a diode and a transistor, utilizing a Si/4H-SiC heteroj unction. A heterojunction diode (HJD) was fabricated with P+ polycrystalline silicon on an N- epitaxial layer of 4H-SiC. The HJD achieved lower Von and higher reverse blocking voltage than a commercial Schottky barrier diode (SBD) of SiC. Switching charcteristics of the HJD indicated almost zero reverse...
High performance LSTP CMISFETs with poly-Si/TiN hybrid gate and high-k dielectric have been studied. Gate depletion is successfully suppressed by in-situ phosphorus doped poly-Si gate for NMIS and by TiN metal gate for PMIS. Vth control for pMIS is accomplished by fluorine implantation into substrate. Optimization of HfSiON formation and TiN removal process is the key to achieve high-reliability....
A solution of utilizing an N-rich SiON gate dielectric toward achieving highly reliable pMOS is demonstrated. The solution consists of a combination of two techniques: (1) a SiN-based gate dielectric with oxygen-enriched interface (OI-SiN) enabling nMOS and pMOS characteristics superior to plasma-nitrided oxides (PNO) and (2) a dual-core-SiON technique in which SiON in pMOS is selectively thickened...
EOT reduction is a key challenge to keep the Moore's law, especially in low power LSIs. Nice candidates of gate dielectric as alternative to conventional SiO2 are N-rich SiON and high-K. However, in each case, we truly need tuning tools of Vth in the system LSI applications. F incorporation technique should be effective in Vth tuning with both N-rich SiON and high-K. Moreover, F incorporation is promising...
In this paper, the authors demonstrate the improvement of HfSiON pFET characteristics with F incorporation technique, which might be a powerful tool to lower Vth in pFET with both poly-Si and PC-FUSI gate. Using F implantation in channel region prior to HfSiON formation Vth lowering up to ~200mV is obtained without mobility degradation. Furthermore, impact of F incorporation in HfSiON is investigated...
Self-formed MnOx barrier technology has been successfully integrated for 150nm pitch Cu dual-damascene interconnects with PAr/SiOC (k=2.65) hybrid structure. Barrier formation at the interface of Cu and various low-k films with few Si or O was confirmed by adhesion, XPS and TEM/EDX analyses. No degradation of interconnect performance and excellent electromigration lifetime were verified. It is concluded...
High performance Ni-FUSI/HfSiON CMIS with suitable Vth in a wide Lg range is presented. This is accomplished by ion implantation to substrate and phase control of Ni-FUSI gate. Threshold voltage of NiSi-FUSI NMIS is controlled by nitrogen implantation, and that of Ni2Si-FUSI PMIS is controlled by fluorine implantation. It is demonstrated that N/F incorporation can realize 0.2-V-low |Vth|, high carrier...
A technique for optimizing ultra-thin (EOT ~ 1.1-1.3 nm) SiON gate dielectrics independently for n- and p-MOSFETs is demonstrated. Selective nitrogen-enrichment for the nMOS and fluorine incorporation to the pMOS regions were both performed by ion implantation into the Si-substrate with resist masks before gate oxidation. The former provided suppression of gate leakage current and enhancement of drain...
A simple high-k/poly-Si dual-gate CMIS platform with a novel method to control threshold voltage (Vth) has been proposed for 45nm node. The PMIS Vth control method is a simple selective fluorine-implantation to channel region with optimizing extension and pocket implantation. We have also demonstrated the transistor variability improvement with our HfSiON/poly-Si platform, compared to SiON/poly-Si...
F incorporation into HfSiON dielectric using channel implantation technique is shown to be highly effective in lowering Vth and improving NBTI in poly-Si gate pFET. Mobility degradation is not accompanied and drive current is increased by 180%. From analytical and electrical characterization, the Vth shift is attributed to change in trap density
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