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The bottle neck of ReRAM (Resistive RAM) for post-NAND storage application is high operational current. Herein, we report a method to acquire low operational currents from a hetero structure ReRAM (AlOx/TiOx). The mechanism study of the hetero structure ReRAM reveals that the AlOx layer as a tunnel barrier is critical for switching, and thus switching parameters are governed by the properties of the...
We have successfully demonstrated a world smallest 0.25 μm2 cell ITIC 64 Mb FRAM at a 130 nm technology node. This small cell size was achieved by scaling down a capacitor stack, using the following technologies: a robust glue layer onto the bottom electrode of a cell capacitor; 2-D MOCVD PZT technology, novel capacitor-etching technology; and a top-electrode-contact-free (TEC-free) scheme. The new...
In order to realize a cost-effective high density FRAM product over 64-Mb, it is inevitable to develop technologies for a small cell and large wafer size without degradation during full integration. We have successfully demonstrated a fully functional 0.16 mum2 capacitor size, 64-Mb, 1T1C FRAM on an 8-inch wafer by introducing new integration technologies at 150 nm technology node. One of the key...
64 Mb FRAM with a 1T1C scheme has progressed greatly for mass production in terms of a highly reliable device. For the first time, package-level reliabilities of the memory were evaluated systematically and massively. The authors scrutinized the device reliabilities in accelerated manners, one of which is high-temperature-operating-life (HTOL) test; and the other is high-temperature-storage (HTS)...
We have successfully demonstrated a 0.34mum2 COB cell 1T1C 64Mb FRAM at 150nm technology node. The minimum signal window between data "1" and data "0" of 64M bit cells was evaluated to 300mV at 85degC, 1.6V VDD. This wide signal window was achieved by introducing advanced anneal technology and optimized capacitor layout, from which the variation of individual cell charge was greatly...
In this paper, data retention loss phenomena after write/erase cycles and time in an embedded SONOS memory cell were investigated for the first time. By analyzing source junction leakage current, it was determined that the loss of holes in nitride also results in an increase in threshold voltage, a drop in ion, and a degradation of sub-threshold slope
We have made great progress for mass production of a highly reliable 1.6V, 0.18 mum 1T1C FRAM embedded smart card. For mass production, our device has to pass standard qualification tests on the package level. These contain the infant life test (ILT), the high temperature operating life (HTOL), the endurance and the high temperature storage (HTS) test. Problems in the PZT capacitor integration scheme...
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