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We propose and experimentally validate an AFD (atomic flux divergence)-based MTTF (mean time to failure) model for wires with EM. We analyze traditional MTTF models and compare them to the proposed model. We use the AFD-based compensation model to quantitatively capture the reservoir effect and provide a relationship between the reservoir's volume and EM lifetime enhancement.
In this paper, we propose a current waveform estimation algorithm for signal lines without the necessity of SPICE simulation. Unlike previous methods, we do not use function fitting or compute the effective capacitance. Instead, the proposed algorithm predicts the current waveform by using current responses of a driver for multiple fixed capacitances provided by the foundry. We demonstrate usefulness...
Electromigration (EM) greatly affects the long-term reliability of VLSI chips. Not only power/ground lines but also bitlines of SRAM arrays may be damaged by EM. In this paper, we analyze current flow on SRAM bitline, demonstrate that it may suffer EM due to the pulsed dc pattern, and conclude that bitline’s EM reliability can dramatically be worsened by process variation due to a significant increase...
In this paper, we study electromigration (EM) reliability of signal lines. We propose a general model for current conversion from pulsed DC to steady DC based on the consistency of maximal atomic flux divergence. Both long and short lead lines with high frequency current are considered. The calculated effective steady DC agrees with the measured results. Our conversion scheme can be applied also to...
Electromigration (EM) greatly affects the long term reliability of VLSI chips. Not only power/ground (P/G) lines, but also bit-lines of SRAM arrays may be damaged by EM. In this work, we demonstrate that the EM reliability of an SRAM array can be dramatically worsened by process variation due to a significant increase of sub-threshold leakage current on the bit-line. We statistically model the effects...
In this paper, we demonstrate that signal lines in SRAM arrays are prone to electromigration (EM). Our analysis shows that the read operation can cause unidirectional current flow in bit-lines. Thus the length of bit-lines should be bounded not only by performance requirements, but also by the Blech length constraint to avoid EM. We propose a method of determining the bit-line width under layout constraints...
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