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Delay test pattern generation has emerged as an increasingly critical problem in high performance VLSI designs. Existing techniques find timing critical paths by STA or SSTA, apply a traditional ATPG algorithm subsequently and find the test patterns. In this paper, we propose a new delay test pattern generation method, which finds timing critical paths by more accurate input-aware statistical timing...
Optimizing energy consumption for electronic systems has been an important design focus. Multi-power domain design is widely used for low power and high performance applications. Data transfer between power domains needs a cross power domain interface (CPDI). The existing level-conversion flip-flop (LCFF) structures all need dual power rails, which leads to large area and performance overhead. In...
We fabricated a low power sensor network processor with Deeply Depleted Channel (DDC) transistors of 65 nm technology, which has distinguishing device structure and enables variation of threshold voltage (Vth) of transistors to decrease. At the optimal voltage condition to achieve the same maximum operating frequency, measurement result shows that the DDC process achieves a 47.0 % of peak power reduction...
Conventional Static Random Access Memory (SRAM) cells suffer from an intrinsic data instability problem due to directly-accessed data storage nodes during a read operation. Noise margins of memory cells further shrink with increasing variability and decreasing supply voltage in scaled CMOS technologies. A selected set of novel seven-transistor (7T) and conventional six-transistor (6T) multi-threshold-voltage...
As proliferation of embedded systems and mobile devices increases, power has become one of the most paramount concerns in current microprocessor designs. Technology scaling has provided many benefits in terms of dynamic power; however, static power has become the bottleneck to reducing power. We address this by evaluating Tunnel FETs (TFETs) for use in low-power, high-performance flip-flop designs...
The mature electronic design automation (EDA) tools and well-defined abstraction-levels for digital circuits have almost automated the digital design process. However, analog circuit design and optimization is still not automated. Custom design of analog circuits and slow analog in SPICE has always needed maximum efforts, skills, design cycle time. This paper presents a novel design flow for constrained...
Rapid passive device modeling is discussed in this work based on test structures fabricated in a 65nm CMOS process with M1–M9 copper metal layers and one aluminum metal layer AP. Capacitance extraction for overlapping microstrips and shielded microstrip structures is investigated. Individual capacitances are modeled in terms of area and fringe components, either between microstrips or between microstrips...
Recently, virtualization techniques has been investigated as an interesting approach for complex embedded systems designs since they allow more secure systems, improve software design quality and reduce costs. However, the need to meet design constraints, mainly the real-time constraints, constitutes one of the biggest challenges that may prevent the wide adoption of virtualization in embedded systems...
This work presents a novel approach to estimate the CMOS inverter delay. The proposed delay model uses the DC transfer curve in order to predict the inverter behavior for slow input transitions rather than estimating the discharging time. Moreover, the only required empirical parameters are those used to calibrate the transistor model. Results are on very good agreement with HSPICE simulations based...
Distributed computing systems have attracted a lot of attention due to increasing demand for high performance computing and storage. Resource allocation is one of the most important challenges in the distributed systems especially when the clients have some Service Level Agreements (SLAs) and the total profit depends on how the system can meet these SLAs. In this paper, an SLA-based resource allocation...
Power Integrity problem for a high speed power plane is discussed in context of selection and placement of decoupling capacitors. The s-parameters data of power plane geometry and capacitors are used for the accurate analysis including bulk capacitors and VRM, for a real world problem. The optimal capacitors and their optimum locations on the board are found using particle swarm optimization. A novel...
In this paper, we focus on power and thermal management for multicore embedded systems with solar energy harvesting as the power source and a periodic hard real-time task set as the workload. We design a novel semi-dynamic scheme, which reschedules tasks at the beginning of specified time epochs. By rejecting job instances of certain tasks until the next rescheduling point, our scheduler dispatches...
Physical Unclonable Functions (PUF) are novel chip identifiers with an extensive array of uses in security applications. In this paper, we propose a novel PUF that has a very large Challenge/Response (C/R) space in a given area, while being resistant to modeling attacks at the same time. We name this design S-ArbRO PUF. We study the variability of the proposed PUF and its reliability to temperature...
This paper presents a novel approach to determine the sensitization probability of a non-robustly testable path using probability density functions (PDFs). The proposed approach systematically refines a set of patterns that sensitize the path non-robustly which initial set has been derived with existing methods, and is kept implicitly. Accurate measure of the sensitization probability is obtained...
Signal and power integrity are crucial for ensuring high performance in high speed digital systems. As the operating frequency of digital systems increases, the power and ground bounce created by simultaneous switching noise (SSN) has become a limiting factor for the performance of these devices. SSN is caused by parasitic inductance that exists in the power delivery network (PDN), and voltage fluctuations...
The performance of standard cells has a strong impact on the performance of a circuit synthesized with the cells. Although a complementary CMOS logic is usually used in the standard cells, it is known that a pass transistor logic can improve the performance of a circuit with a smaller area in some cases. We evaluate different types of XOR cells in different voltage conditions. Results show that the...
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