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A low-cost low-power baseband processor for passive UHF RFID Tag based on EPC C1G2 protocol is presented in this paper. In order to minimize the power consumption, a novel digital baseband architecture is proposed and a series of low-power design approaches are adopted, including asynchronous design, clock-gating, low operating frequency, reuse of registers, etc. The baseband processor supports eleven...
A new gate controlled bipolar transistor is introduced in this paper which combines the lateral and vertical bipolar effect in standard NMOS device in a 90 nm triple well process technology. A current gain of more than 200, cut off frequency of about 7 GHz, and lower flicker noise compared with CMOS devices were achieved without any change to process and/or introduction of any extra masking step....
We present here experimental measurement and modeling of drain current thermal noise in a 90 nm CMOS technology, with a focus on its current dependence. For the first time we show experimental evidence that drain current noise in weak inversion is indeed shot-like (2ql). In saturation, drain current noise is mainly determined by the drain current, and only weakly dependent on the drain voltage. A...
This work examines the differences between the gd0 and gm referenced drain current excess noise factors in CMOS transistors as a function of channel length and bias. Using standard linear noisy two-port theory, we present a simple derivation of noise parameters. The results are compared with the well known Fukui's empirical FET noise equations. Experimental data on a 0.18 mum CMOS process are measured...
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