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The introduction of mammalian species such as rats, stoats and possums into New Zealand has proven devastating to what was once a pristine ecosystem. Unlike the accidental introduction of rats and stoats, Possum were introduced with the intention of establishing a fur trade. Pest populations rapidly grew with an abundance of vegetation and few predators. As a result, rats, stoats and possums have...
In this paper, by using comprehensive statistical device simulation methodology, we investigate the effect of Statistical variability and reliability on the state of the art 14nm FinFET technology on important device figures of merit. Important sources of statistical variability have been considered in all simulation of fresh devices and various degradation levels are included in the reliability simulation...
In this work we have investigated the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future applications. For the purpose of this paper we have simulated Si NWTs with six different cross-section shapes. However for all devices the cross-sectional area is kept constant in order to provide fair comparison. Additionally we have...
Embedded non-volatile memory (NVM) introduces additional thermal processes to a logic process flow and the impact from this extra thermal budget becomes more considerable with continued device scaling. This paper investigates the mechanism of SRAM VMIN degradation in a 40nm embedded NVM process and provides a solution to address the degradation caused. Failure analysis shows enlarged poly grain size...
InGaAs gate-all-around (GAA) MOSFETs with implanted source and drain (S/D) structure have been demonstrated which offer large drive currents and excellent immunity to short channel effects down to deep sub-100 nm channel length [1–2]. In this work, we fabricate n++ raised S/D InGaAs GAA MOSFETs with 10nm or 20nm thick nanowires and 200nm channel length. Maximum Ion over 1 mA/μm at Vgs-Vt=1V and Vds...
We report a systematic study on the impact of process and statistical variability on SRAM design in a 14nm SOI FinFET technology node. A comprehensive statistical compact modelling strategy is developed for the early delivery of reliable PDK model, which enables TCAD-based transistor-cell co-design and path finding during the early phase of a technology node.
Strained silicon germanium (sSiGe), as channel materials, has received a lot of attention due to its high hole mobility [1]–[4]. sSi/sSiGe/sSOI heterostructure substrate [5]–[8] takes the advantages of the tensile strained Si layer, and thus can increase the critical thickness for pseudomorphically grown SiGe with high Ge concentration. In this work, QW p-MOSFETs [9]–[11] on sSi/sSi0.5Ge0.5/sSOI substrate...
Reversible switching of an optical gate based on Si rib waveguides with a Ge2Sb2Te5 thin film is reported. We demonstrated four cycles of switching by pulsed laser irradiation. The average extinction ratios of each switching event were 9.1, 10.7, 11.6 and 11.7 dB, respectively. The extinction ratio of this optical gate was more than 5.9 dB over the wide wavelength range from 1525 nm to 1600 nm.
Adequate ESD protection is a new design challenge for HV electronics. This paper presents design, failure analysis and optimization of a HVggLDMOS ESD protection structure in a HV BCD process. Theoretical analysis involving Kirk effect and mixed-mode ESD simulation-design technique were used to analyze experimental results and to optimize the HV ESD protection structure.
P-MOSFETs with HfO2 gate dielectric and TiN metal gate were fabricated on compressively strained SiGe layers with a Ge content of 50 at.% and electrically characterized. The devices showed good output and transfer characteristics. The hole mobility, extracted by a split C-V technique, presents a value of ~200 cm2/V·s in the strong inversion regime.
Nano Beam Diffraction has been used to analyze the local strain distribution in MOS transistors. The influence of wafer process on the channel strain has been systematically analyzed in this paper. The source/drain implantation can cause a little strain loss but the silicidation step is the key process in which dramatic strain loss has been found.
Metal-insulator-semiconductors structures (MIS) with a layer of silicon nanocrystals embedded within two SiO2 layers are fabricated by using plasma enhanced chemical vapor deposition. By using current-voltage (I-V) measurements with different sweep rates, we study the mechanism of electrons and holes charging/discharging characteristic of the MIS structures. Distinct current peaks duo to electrons...
Statistical variability (SV) presents increasing challenges to CMOS scaling and integration at nanometer scales. It is essential that SV information is accurately captured by compact models in order to facilitate reliable variability aware design. Using statistical compact model parameter extraction for the new industry standard compact model PSP, we investigate the accuracy of standard statistical...
This paper presents a new impulse based ultra-wide band (UWB) transceiver system designed in 90nm CMOS technology for UWB medical radar sensing and communication applications. The design is targeting for human heart motion detection and short range data communications. The transmitter is composed of a simple on-off keying (OOK) modulated impulse generator and a variable gain-controlled amplifier (VGA)...
A compact Marx generator has been developed by using power MOSFETs as the switches. The objective is to develop repetitive, compact, efficient, short-pulse, high-voltage generator for industrial applications. The initial tests were carried out by using 16 switches, achieving output of ~ 10 kV and ~ 250 ns in pulse width at repetition rate of ~ 400 Hz.
CMOS devices with high-k/metal gate stacks have been fabricated using a gate-first process flow and conventional stressors at gate lengths of 25 nm, highlighting the scalability of this approach for high performance SOI CMOS technology. AC drive currents of 1630muA/mum and 1190muA/mum have been demonstrated in 45 nm ground-rules at 1V and 200nA/mum off current for nFETs and pFETs, at a Tinv of 14...
For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V Vdd with a low cost process. With this high performance transistor,...
At the 22 nm node, we estimate that superior electrostatics and reduced junction capacitance in FinFETs may provide a 13~23% reduction in delay relative to planar FETs. However, this benefit is offset by enhanced gate-to-source/drain capacitance (Cgs) in FinFETs. Here, we measure FinFET Cgs capacitance at 22 nm-like dimensions and determine that, with optimization, the FinFET capacitance penalty can...
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