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In this paper, we investigate reliability testing for a glass interposer. The test vehicle is an assembled glass interposer with a chip, a BT substrate. The structure of a glass interposer with two redistribution layers (RDLs) on the front-side and one RDL on the back-side has been evaluated and developed. Key technologies, including via fabrication, front-side RDL formation, microbumping, temporary...
With the rapid development of electronics industry, the printed circuit board (PCB) is the most important indispensable components for various kinds of products such as military, medical, appliances and consumer electronics. At the beginning, the construction of integration of electronic components by PCB process is single layer and double layer process. Until now, the yield of multilayer process...
In this paper, we investigated the reliability test for Glass interposer. The test vehicle is assembled glass interposer with chip, BT substrate, and PCB. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside had been evaluated and developed. Key technologies, including via fabrication, topside RDL formation, micro-bumping, temporary bonding, silicon and glass...
Flip chip package has been reported to be an ideal package solution of high bandwidth devices because of a lower power loss and a short transmission route of signal. However, some failure modes such as solder joint crack, delamination of substrate or low-k delamination within IC were often found after reliability verification. One of the key factors of failure is attributed to the mismatch of CTE...
In this paper, we investigated the assembly characterization for reliability test. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside had been evaluated and developed. Key technologies, including via fabrication, topside RDL formation, micro-bumping, temporary bonding, glass thinning and backside RDL formation, were developed and integrated to perform well...
In this investigation, a SiP (system-in-package) which consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top- and bottom-side (a real 3D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top-chip, bottom-chip, TSH interposer,...
Glass interposer is proposed as a superior alternative to organic and silicon-based interposers for 3DIC packaging in the near future. Because glass is an excellent dielectric material and could be fabricated with large size, it provides several attractive advantages such as excellent electrical isolation, better RF performance, better feasibility with CTE and most importantly low cost solution. In...
In this investigation, a system-in-package (SiP) that consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top and bottom sides (a real 3-D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top chip, bottom chip, TSH interposer,...
A double-sided Si passive interposer connecting active dies on both sides for a 3D IC integration is investigated. This interposer is 100μm-thick with 10μm-diameter TSVs (through silicon vias), 3 RDLs (redistribution layer) on its front-side, 2 RDLs on its backside. It supports 2 active dies on its frontside and 1 active die at its backside. The present study focuses on the process integration of...
As the demands for high density 3DIC stacking increase, a fine-pitch chip-to-chip interconnects is becoming imperative. In conventional flip-chip technology, anisotropic conductive film (ACF) has been used in place of solder and underfill for chip attachment to substrates in some applications, because it provides many advantages. Generally speaking, ACF consists of an adhesive polymer matrix with...
In this study, a 3D IC integration system-in-package (SiP) with TSV/RDL/IPD interposer is designed and developed. Emphasis is placed on the Cu revealing, embedded stress sensors, non-destructive inspection, thermal modeling and measurement, and final assembly and reliability assessments.
The board-level reliability of a 6-layer polyimide-based coreless flip chip package assembled on a printed circuit board (PCB) under a temperature cycling condition of -55 ~ 125??C was investigated in this study. The assembly of coreless flip chip package was achieved by a 17 mm ?? 17 mm die with 4355 Sn37Pb solder bumps, an amine-based underfill and 1521 Sn3.0Ag0.5Cu solder balls, no defect such...
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