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In this paper, a 5kW novel multistage axial-flux permanent magnet machine (M-AFPM) is analyzed. As a key part of the machine, stator core of silicon steel and SMC are studied by 3D finite element method (FEM) respectively. No-load, full-load, magnetic field distribution, core loss, etc. are calculated. FEM result indicates that SMC-materials have almost equal influence on EMF, magnetic field distribution...
TSV (through silicon via) is regarded as a key technology for 2.5D and 3D electronic packaging. And the manufacturing of the through silicon interposer is very challenge and costly. In the backside process of interposer, grinding is considered as the most promising technology to control wafer's surface roughness and surface defect. In this paper, according to the grinding process, a mathematical model...
Temporary bonding and release processes are regarded as the critical technologies in 2.5D and 3D IC integration. The process is especially challenging when the device contains high topography structures like copper pillar bumps. This paper presents the results of simulation, bumping process, wafer temporary bonding, thinning and debonding. Through careful consideration and optimization of the above...
This paper presents signal integrity analysis of a high-performance processor package with silicon interposer. Thediewas attached on the top side of the siliconinterposer with through silicon vias (TSVs), and theinterposer was connected to the organic substrate. The signal transmission path of this package consists of two redistribution layers (RDLs), TSVson interposer, and wirings on the substrate...
Through glass via (TGV) technology is considered to be a cost effective enabler for micro electromechanical systems (MEMS) and radio frequency (RF) system-in-package (SIP) technology. Inductively coupled plasma (ICP) and the Bosch etching process comprise one of the most pervasive methods for via formation in silicon. Unfortunately an equivalently process for glass remains elusive. In this paper,...
TSV (through-silicon-via) has been regarded as a key technology for 2.5D and 3D electronic packaging. However, the manufacturing of the through silicon interposer (TSI) is very challenging and costly. The minimization of the warpage of the TSV interposer wafer is crucial for successful subsequent processing, for example, thin wafer handling, backside via revealing and copper pillar bumping. In this...
TSV (through silicon via) is regarded as a key technology for 2.5D and 3D electronic packaging. And the manufacturing of the through silicon interposer is very challenge and costly. In the backside process of interposer, grinding is considered as the most promising technology to control wafer's surface roughness and surface defect. In this paper, according to the grinding process, a mathematical model...
Through glass via (TGV) technology is considered to be a cost effective enabler for micro electromechanical systems (MEMS) and radio frequency (RF) system-in-package (SIP) technology. Inductively coupled plasma (ICP) and the Bosch etching process comprise one of the most pervasive methods for via formation in silicon. Unfortunately an equivalently process for glass remains elusive. In this paper,...
Temporary bonding and release processes are regarded as the critical technologies in 2.5D and 3D IC integration. The process is especially challenging when the device contains high topography structures like copper pillar bumps. This paper presents the results of simulation, bumping process, wafer temporary bonding, thinning and debonding. Through careful consideration and optimization of the above...
This paper presents signal integrity analysis of a high-performance processor package with silicon interposer. Thediewas attached on the top side of the siliconinterposer with through silicon vias (TSVs), and theinterposer was connected to the organic substrate. The signal transmission path of this package consists of two redistribution layers (RDLs), TSVson interposer, and wirings on the substrate...
TSV (Through Silicon Via) is regarded as the key enabling technology for 2.5D and 3D IC packaging solution. Si interposers with TSV have emerged as an excellent solution providing high wiring density interconnection, minimizing CTE mismatch to the Cu/low-k chip that is vulnerable to thermo-mechanical stresses, improving electrical performance and decreasing power consumption due to shorter interconnection...
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