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In this work we investigate the correlation between hydrogen content and leakage current through the Al2O3 layers of TANOS memories. We put in evidence that retention of TANOS memories is improved with the decrease of H concentration in the Al2O3 layer. Using atomistic simulations consolidated by detailed Al2O3 physico-chemical analyses, we find that interstitial H produces a midgap trap likely to...
We fabricated CMOS devices on Ultra-Thin Boby and Buried Oxide SOI wafers using a single mid-gap gate stack. Excellent global, local and intrinsic VT-variability performances are obtained (AVT=1.45mV.μm). This leads to 6T-SRAM cells with good characteristics down to VDD=0.5V supply voltage and with excellent Static Noise Margin (SNM) dispersion across the wafer (σSNM<;SNM/6) down to VDD=0.7V. We...
In this work we present the integration of Band Engineered TANOS-like memories using HfSiON in the tunnel stack to boost the programming efficiency and improve cycling. An accurate correlation analysis between the gate-stack material physical properties and the memory performances is presented. In particular, the importance of the nitridation step of HfSiON on the memory retention characteristics...
The integration of silicon nanocrystal (Si-nc) nonvolatile memory (NVM) arrays with HfAlOx based interpoly dielectric (IPD) is presented for the first time. The data obtained on array vehicles programmed in Fowler-Nordheim operation regime are in excellent agreement with previously presented results on single cells, as well as theoretical data and allow the evaluation of the scalability of the Si-nc...
In this paper, different Hf-based oxides (HfO2, HfSiO under several annealing conditions, HfSiON, HfAlO with various compositions) are simultaneously considered as storage layers of charge-trap memories. Based on material characterization analyses, electrical data of memory cells, physical modeling of charge-trap devices, we show that a strict relationship exists between the crystal structure of the...
Replacing the tunnel oxide of non-volatile memories by a high-k dielectric is addressed in this paper. This work reports in its first part an experimental study of conduction and trapping in Al2O 3 layers. The experimental data of these layers is then integrated in a novel endurance model suitable for flash memories with high-k tunnel oxide. Simulation results show that low (+8/-7V) operating voltages...
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