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Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and are susceptible to undergo defects at different stages: during their own fabrication, the bonding stage or during their life time. Typical defects are microvoids, underfilling, misalignement, pinholes in the oxide or misalignments during bonding in such a way that resistive opens become a frequent...
Digital approaches concerning the I/Q imbalance problem in zero-intermediate frequency (zero IF) mixing scheme have one of two main objectives: the first one is knowing the parameters of a widely—linear system (WLS) that models this problem with the purpose of devising a compensation scheme (calibration). The second one is estimating the system gain and phase imbalance values before and after calibrating...
The continues improvement of manufacturing technologies allows the realization of integrated circuits containing an ever increasing number of transistors. A major part of these devices is devoted to realize SRAM blocks. Test and diagnosis of SRAM circuits are therefore an important challenge for improving quality of next generation integrated circuits. This paper proposes a flexible platform for testing...
In order to compare current and logic testing of a static memory cell in the presence of bridging defects, an electrical model for the defective cell is used. The SPICE parameters for the cell have been extracted from the layout and process information. All the extracted bridges are shown to be quiescent current testable. However, for a large percentage of the defects, the logic (voltage) testability...
Bridging faults have been shown to be a major failure mode in CMOS IC's [SHE85]. A model that takes into account the different resistance values of the bridge is presented. This model is used to estimate the IDDQ range of values to evaluate the possibility of current testing of this fault [NIG90]. A simple circuit is used as an example. This methodology is demonstrated to provide a greater domain...
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