The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The behaviour of a defective CMOS latch cell with floating gate defects is analysed in order to investigate the detection of these defects by logic testing. A large number (40%) of the defects will never be detectable by logic testing. Some of the remaining floating gate defects are also undetectable by logic testing, depending on their defect topologies. The need for other test methods such as I/sub...
Bridging faults have been shown to be a major failure mode in CMOS IC's [SHE85]. A model that takes into account the different resistance values of the bridge is presented. This model is used to estimate the IDDQ range of values to evaluate the possibility of current testing of this fault [NIG90]. A simple circuit is used as an example. This methodology is demonstrated to provide a greater domain...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.