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In this paper, a new simplify mismatch of temperature and narrow channel dependence of threshold voltage of NMOS developed from spice level 3 and BSIM3 are proposed. The IDS -VGS in linear region was used with a different channel width. The parameters extraction procedure is based on the measurement of the transconductance characteristics of MOSFET in linear region. In this model, the temperature...
The CMOS fabrication technology requires both n-channel (NMOS) and p-channel (PMOS) transistors be built on the same substrate. To ensure the reliability of the circuit performance over the temperature range, the circuits must be designed accommodate the basic variations parameters as a function of parameter. The temperature dependence of the MOSFET parameters as well as the small dimension effects...
A MOS-diode biased by a constant inversion level current source is a simple MOSFET-only circuit that implements a voltage source with a linear temperature dependence. Through adjustment of the inversion level, the temperature slope may be changed from negative to positive, including the constant voltage condition. A test circuit, fabricated on a 0.35μm CMOS technology, was measured from 300K to 375K...
In this paper, we analyze, for the first time to our best knowledge, the high-temperature perspectives of Ultra-thin body (UTB) SOI MOSFETs. High-temperature behavior of threshold voltage, subthreshold slope, transconductance maximum and on-current is analyzed in details through measurements and 2D simulations. Particular attention is paid to the effect of buried oxide (BOX) and Si film thicknesses...
The Zero Temperature Coefficient (ZTC) is investigated experimentally in planar and standard/biaxially strained triple-gate nFinFETs fabricated on SOI wafers. In this work a simple model to analyze the behavior of the gate-source voltage at the Zero Temperature Coefficient point (VZTC) is proposed in the linear and saturation operation regions. The analysis takes into account the temperature variations...
Quantum well (QW) FETs with compressively-strained SiGe channel are promising candidates for pMOSFET for future logic technology with scaled operating voltage. High hole mobility observed in strained SiGe channel layer, as compared to Si, is expected to result in enhanced performance of these devices for deep submicron channel lengths. However, most of experimental results in literature so far, focusing...
This paper presents the design of a voltage reference cell suitable for low-voltage and low-power applications without the usage of bipolar structures. The respective reference voltage can be trimmed within a certain range to compensate the unavoidable process variations. The chip is designed based on a 0.13 μm CMOS technology.
Power-supply/temperature-variation-aware circuit components, such as a current source and a comparator, based on adaptive reference-voltage control are proposed for robust multiple-valued current-mode (MVCM) circuits.Since the reference-voltage level generated by the proposed reference-voltage generator is changed in proportion to the power supply, the gate-source voltage VGS of PMOS transistor at...
Reported here are subthreshold measurements on n-channel 6H-SiC MOSFETs over a range of temperatures. A simple theoretical model is presented to explain their general form. It is shown that the temperature dependence of the subthreshold current indicates a high density of electronic states at or near the SiC-SiO2 interface. These states are negatively charged when occupied (acceptor-like), and emit...
In this work, we investigate the channel backscattering characteristics for SOI MOSFETs using a new temperature-dependent method with consideration of self-heating effects. The temperature sensitivity of mobility (beta, mu0propTbeta) is self-consistently determined along with the backscattering coefficient rsat.
MOSFET's with gate lengths down to 0.1 ??m were characterized at low temperatures. Below 20 K, characteristic peaks in the transconductance were observed in weak and moderate inversion at low drain voltages. This result can be explained by quantum transport mediated by localized states in the channel.
The degradation of MOSFET's due to hot carrier stress is described quantitatively by trapping of die injected carriers a density of traps NT with a capture cross section ??. The temperature- and field-dependence of ?? strongly affects the stress behavior for electron and hole injection. The time dependence of the generation of fixed oxide charge and interface states suggests different mechanisms for...
An analytical model of the kink effect in MOS transistors is proposed. This model procures a comprehensive view of the kink effect in bulk silicon MOSFETs and, subsequently, in SOI devices. It is shown both experimentally and theoretically that the excess drain current induced by the kink effect is proportional to the body transconductance of the device operated at room as well as liquid helium temperatures.
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