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The IEEE 1687 Standard specifies an access network and a description language for embedded instruments. In this paper, we present an optimization technique to minimize the segment insertion bit (SIB) programming overhead for IEEE 1687-compliant access architectures. We first present an optimal solution based on dynamic programming for concurrent access schedules. This technique is then utilized to...
In this work, a novel design and optimization method for programmable gate macro blocks (PGMB) in the newly proposed Asynchronous Nanowire Reconfigurable Crossbar Architecture (ANRCA) is presented. ANRCA is based on a self-timed logic referred to as the Null Convention Logic (NCL). Since there is no global clocking and clock distribution network, all failure modes related to timing will be either...
In this work, a novel model-based latency/area measurement and optimization method for the newly proposed Asynchronous Nanowire Reconfigurable Crossbar Architecture (ANRCA) is presented and validated. ANRCA is based on a self-timed logic referred to as the Null Convention Logic (NCL). Since there is no global clocking and clock distribution network, all failure modes related to timing will be either...
In this work, we have compared different FB-RAM architectures. Whereas highly doped PDSOI devices show high programming window and retention times for long channel devices, the SOI FinFET devices with WFIN=25 nm can be scaled down to LG=50 nm while still maintaining high cell margins and retention times. For the latter devices optimization of the write and especially read bias conditions is needed.
This paper presents a systematic methodology to design efficient sub-90-nm split-gate Flash-memory cells and optimize the cell performance within the presently known scaling constraints. The device-simulation results show that the high-performance sub-90-nm split-gate cells can be realized by a proper optimization of the channel and asymmetric halo-doping profiles and shallow source/drain junctions...
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