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This study proposes an efficient very large scale integration (VLSI) architecture for quadruple throughput fixed point multiply accumulate circuit (MAC). The proposed n × n bits MAC is used to perform one n × n bits or two n × (n/2) bits or four (n/2) × (n/2) bits MAC operations in parallel. The objective of the proposed MAC is to improve throughput of the existing MAC designs. The proposed and existing...
Latency, Area, and Power are three important metrics that a VLSI designer wants to optimize. However, often one of these may have to be optimized at the cost of another or the other two. Depending on the application scenario, choice of the metric to optimize is made. In this paper, we consider hardware implementations of a number of cryptographic primitives and present a number of optimizations. We...
This paper proposes an efficient VLSI architecture for discrete Hadamard transform, which is used in real time digital signal processing applications like image coding, MPEG, and CDMA etc. The proposed N-point Hadamard transform architecture consists of signed carry save adder tree. So the depth of the architecture falls within the bounds of O (log2 N). The same proposed architecture is implemented...
This paper proposes a novel fixed point multiplier architecture with data level parallelism. That is, the same multiplier hardware is used to perform multiple multiplications on different data paths. Here, we proposed a Wallace tree multiplier to perform more number of multiplications in parallel with fewer extra carry save stages than conventional multiplier. The proposed n-bit Wallace structure...
This paper proposes a novel fixed point complex number multiply accumulate circuit, which is used in real time digital signal processing applications. The proposed architecture consists of multiplier-cum-accumulator which can be used as multiplier as well as MAC. Here the previous MAC result is added as one of the partial products of the current multiplication. So the depth of the multiplier-cum-accumulator...
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