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This paper reports on one of the first demonstrations of the formation and metallization of 2–5-$\mu \text{m}$ lines and spaces by an embedded trench method in two dry-film polymer dielectrics, Ajinomoto build-up film and preimidized polyimide, without using chemical mechanical planarization. The trenches and vias in 8–15-$\mu \text{m}$ -thick dry-film dielectrics were formed by 308-nm excimer...
Comprehensive investigations were conducted on identifying integration efforts needed to adapt plasma dicing technology in BEOL pre-production environments. First, the authors identified the suitable process flows. Within the process flow, laser grooving before plasma dicing was shown to be a key unit process to control resulting die sidewall quality. Significant improvement on laser grooving quality...
Ultra-thin, panel-level glass fan-out packages (GFO) were demonstrated for next-generation fan-out packaging with high-density high-performance digital, analog, power, RF and mm-wave applications. The key advances with GFO include: 1) large area panel-scalable glass substrate processes with lower cost, 2) silicon-like RDL on large panels with 1-2 µm critical dimensions (CD), 3) lower interconnect...
This paper presents the design and implementation of engineered nanoscale bonding interfaces as an effective strategy to improve manufacturability of Cu-Cu bonding to the level where it can, for the first time, be applied to chip-to-substrate (C2S) assembly. All-Cu interconnections are highly sought after to meet the escalating electrical, thermal, and reliability requirements of a wide range of emerging...
This paper reports the demonstration of 2-5 µm embedded trench formation in dry film polymer dielectrics such as Ajinomoto build-up film (ABF) and Polyimide without using chemical mechanical polishing (CMP) process. The trenches in these dielectrics were formed by excimer laser ablation, followed by metallization of trenches by copper plating processes and overburden removal with surface planer tool...
This paper describes the improvement of advanced semi-additive processes (SAP) to demonstrate 1.5-5 µm lines and spaces with 4-5 µm diameter photo-vias for multiple re-distribution layers (RDL) at 20 µm bump pitch on glass interposers. High performance computing systems for networking and graphics are driving ultra-high bandwidth interconnections between logic and memory devices. This signal bandwidth...
A suite of highly precise surface planarization equipment and associated unit process have been developed for several years. Recent studies showed that this process is suitable to address the persistent needs for improved planarity of surface topographies and bonding interfaces during advanced packaging fabrications and assembly. Myriad process capabilities have been achieved to date on both wafer-level...
The authors evaluated various dicing methods in order to improve the TCT reliability against SeWaRe type of failures in glass interposers fabricated by polymer lamination over thin glass sheet cores. For blade-based dicing methods, the criteria for down-selection were (i) the least glass sidewall roughness and (ii) crack-free die edge visual inspections. In this fashion, a BKM dicing blade was identified...
As 3DIC with through silicon vias (TSV) approaches high volume manufacturing readiness the importance of precision backgrinding has become increasingly more evident. Active management of the backgrinding process has multiple benefits in that it reduces the risk of wafer backside contamination due to premature contact with vias, it enables optimization of the post-thinning residual silicon thickness...
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