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The tunable negative differential resistance (NDR) characteristics of metal–insulator–semiconductor–insulator–metal (MISIM) tunnel diodes (TDs) structure with thin oxide were observed by biasing the substrate simultaneously with one of the TDs under designed voltage drops ($\Delta \text{V}$ ). An inner circular electrode TD surrounded by a ring-shape electrode TD gate pattern was adopted. The NDR...
In recent years, the 2.5D IC (Integrated Circuit) package with TSV (Through Silicon Vias) has become important for high-bandwidth and high-performance applications. It is well known that 2.5D technology requires significant innovation in the areas of process technology, packaging, design, thermals, and test solutions leading to several hundred new technologies in a single product. With these complex...
Fan-out chip on substrate (FOCoS) is defined as the fan-out package flip-chip mounts on high pin counts ball grid array substrate. 12-inch advanced wafer level package (aWLP) process is implemented on FOCoS for cost saving advantage. The fan-out package constructs from multi-chips with short interconnection between die to die (D2D) by re-distribution layer (RDL) process, which has the potential for...
The Embedded die in substrate (EDS) market has grown significantly over the past several years and it is now one of the fastest growing packaging technologies in the semiconductor industry driven by smaller form factor, better heat dissipating, low noise emission, higher levels of integration and better performance. In addition, for power management and mobile-wireless application the embedded technology...
Commercial values of the relevant optical products are very potential in the future because more and more applications are successfully used in many fields. Currently, there several solutions are developing in Advanced Semiconductor Engineering of Chungli and Kaohsiung (ASE CL and KH), especially concentrating on the optical sensor and transceiver. Regarding the optical sensor transceiver, the edge-emitting...
The present paper introduced a non-destructive TDR (Time Domain Reflectomerty Analysis) methodology, an essential E-FA (Electrical Failure Analysis) technique for separating the fault isolation and identifying failure mode of advanced 2.5D IC package. The package consists of TSV and u-bump staked packaging structure. This methodology has been shown to be applicable for allocating the defect within...
This article makes research on novel metasurface with randomly distributed reflection phase, which are expected to effectively reduce radar cross-section (RCS) of conducting objects. We have realized an instance of such metasurface, which is composed of three-layer stacked-patch elements. The RCS-reduction feature of this instance is validated by measurements under normal plane wave incidence. It...
As the miniaturization of electronic products leads the trend, the dimensions of the solder joints devote to scaling down. With decreasing the size of the solder bump, the current density gets higher. EM becomes a serious reliability issue. The general bump pitch of the solder bump is reduced from 270 μm to below 150 μm due to the demand of miniaturization. In this work, the influence of two Ag-contents...
The industry saw the transition of flip chip technology from lead free solder system to Cu pillar bump a few years ago. The risk of fail location under electromigration (EM) shifts from the solder/UBM interface of the standard solder bump to the solder joint of the Cu pillar solder joint. This study investigated the performance of the Cu pillar solder interconnect under current stress testing and...
A potential technology by substrate interposer enables high bandwidth and low power application processing devices of the future, because the demand of smart mobile products are driving for higher logic-to-memory bandwidth (BW) over 30 GB/s with lower power consumption and ultra-capacity of memory. This paper presents a new High Bandwidth Package-on-Package (HB-PoP) structure with substrate interposer...
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