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Scan based diagnosis plays a critical role in yield enhancement of sub-nanometer technology based chips. However, the scan chain itself can be subject to defects due to the large logic circuitry associated with it which constitute a significant fraction of total chip area. In some cases, it has been observed that scan chain failures may account for 30% to 50% of chip failures. Hence, scan chain testing...
Almost every complex circuit today employs scan-based Design-for-Testability (DFT) architecture to enhance controllability and observability for every flip-flop in the design, thereby improve the testability. However, the DFT structure can also be exploited to mount side-channel attacks to retrieve the secret key stored in a cryptographic chip, thus compromising its security. In this paper, we propose...
Delay defects can be detected using Launch-off-capture (LOC) and Launch-off-shift (LOS) based delay test techniques. In terms of delay test coverage and test set size, LOS is more effective compared to LOC. However, to exercise LOS test a high speed scan enable signal is required. The cost of implementing a high speed global scan enable signal is prohibitively high. In practice, most of the commercial...
Over the years, serial scan design has became the defacto Design for Testability (DFT) technique. The ease of testing and high test coverage has made it to gain wide spread industrial acceptance. However, there are associated penalties with serial scan. These penalties include performance degradation, test data volume, test application time, and test power dissipation. The performance overhead of...
Scan test time has always been one of the priority issues for test researchers because it directly impact cost of the design. In this work we have addressed the issue through scan chain and test pattern reordering. The idea of limited scan shift is explored. We have proposed a graph theoretical framework for reordering of scan chain and test pattern. Graph theoretic problem is formulated for each,...
Power dissipation during scan testing of modern high complexity designs could be many folds higher than the functional operation power, which is a well established observation. High test power dissipation can severely affect the chip yield and hence the final cost of the product. This makes it of utmost important to develop low power scan test methodologies. In this work we have proposed a modified...
The demand for high performance system-on-chips (SoC) in communication and computing has been growing continuously. To meet the performance goals, very aggressive circuit design techniques such as the use of smallest possible logic depth are being practiced. Replacement of normal flip-flops with scan flip-flops adds an additional multiplexer delay to critical path. Furthermore as the combinational...
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