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A promising high-voltage MOSFET (HVMOS) is experimentally demonstrated in 28nm Ultra-Thin Body and Buried oxide Fully Depleted SOI technology (UTBB–FDSOI). The Dual Ground Plane Extended-Drain MOSFET (DGP EDMOS) architecture uses the back-gate biasing as an efficient lever to optimize high-voltage performances. The idea is to implement two different ground planes under the device to control separately...
We have already demonstrated the fabrication of a Dual-Ground Plane Extended Drain MOSFET with 28nm FDSOI technology. The detrimental consequences of ultrathin SOI film were mitigated by back-biasing the ground planes. In this paper, we explore for the first time the device optimization in 28 nm FDSOI node by doping the drift region. This solution requires additional and dedicated process steps but...
A promising high-voltage MOSFET (HVMOS) in Ultra-Thin Body and Buried oxide Fully Depleted SOI technology (UTBB-FDSOI) is experimentally demonstrated. The Dual Ground Plane Extended-Drain MOSFET (DGP EDMOS) architecture uses the back-gate biasing as an efficient lever to optimize high-voltage performances. We show that the separated biasing of the two ground planes enables independent control of the...
Based on systematic measurements in CMOS 40nm bulk technology, we propose a new model for isolated Extended-Drain MOS (EDMOS) transistor. Our custom Spice macro-model includes main specific effects in high-voltage devices. In particular, the model accounts for the various parasitic bipolar components (PBCs) that are fully characterized. This model can cover various architectures, from bulk-Si to FDSOI.
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