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This paper demonstrates a high performance brain-computer interface (BCI) that allows users to dial phone numbers. The system is based on Canonical Correlation Analysis (CCA) and the automatic artifacts removal system based on BSS-CCA method and Steady-State Visual Evoked Potential (SSVEP). Through six frequency bands (9Hz, 10Hz, 11Hz, 12Hz, 13 Hz, 14Hz) displayed on the screen, subjects can choose...
This paper demonstrates a high performance brain-computer interface (BCI) that allows users to dial phone numbers. The system is based on Canonical Correlation Analysis (CCA) and Steady-State Visual Evoked Potential (SSVEP). Through six buttons (9Hz, 10Hz, 11Hz, 12Hz, 13 Hz, 14Hz) displayed on the screen, subjects can choose the number by gazing at the computer interface. This proposed EEG (Electroencephalography)...
This paper presents an efficient VLSI implementation of a singular value decomposition (SVD) processor of on-line recursive independent component analysis (ORICA) for use in a real-time electroencephalography (EEG) system. ICA is a well-known method for blind source separation (BBS), which helps to obtain clear EEG signals without artifacts. In general, computations of ORICA are complicated and the...
This paper demonstrates a high performance brain-computer interface (BCI) that allows users to dial phone numbers. The system is based on Canonical Correlation Analysis (CCA) and Steady-State Visual Evoked Potential (SSVEP). Through six frequency bands (9Hz, 10Hz, 11Hz, 12Hz, 13 Hz, 14Hz) displayed on the screen, subjects can choose a phone number by gazing at the display interface. This proposed...
This paper presents a real-time processing flow for ICA based EEG acquisition system with eye blink artifact elimination. Since EEG signals are one of the feeblest physiological electrical signals, it is easily contaminated by artifacts. Previously, ICA was used to extract artifacts from an EEG data segment in a time period. After processing of ICA, automatic artifact detection and elimination are...
This paper presents a pipeline VLSI design of fast singular value decomposition (SVD) processor for real-time electroencephalography (EEG) system based on on-line recursive independent component analysis (ORICA). Since SVD is used frequently in computations of the real-time EEG system, a low-latency and high-accuracy SVD processor is essential. During the EEG system process, the proposed SVD processor...
This paper presents a parallel VLSI architecture of a singular value decomposition (SVD) processor for real-time multi-channel electroencephalography (EEG) System. In the recent years, EEG has been widely applied on engineering research, medical diagnosis, and so on. More and more studies regarding brain-computer interface (BCI) and other related applications have been published. In order to increase...
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