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This paper proposes a method to reduce the supply voltage IR drop of 3D stacked-die systems by implementing an on-chip Buck Converter on Top die (BCT) scheme. The IR drop is caused by the parasitic resistance of Through Silicon Vias (TSV's) used in the 3D integration. The IR drop reduction and the overhead associated with the BCT scheme are modeled and analyzed. A 3D stacked-die system is manufactured...
A “scalable 3D-FPGA” using TSV interconnects is proposed. This FPGA was designed on the basis of homogeneous 3D-stacking to extend the logic scale in proportion to the number of stacked layers. To improve Z-axis transmission performance, a wafer-to-wafer stacking process for lowering the capacitance of TSV was developed. An “embedded TSV“ design for the shorter on-chip wirings was also devised. Moreover,...
A “scalable 3D-FPGA” using TSV interconnects is proposed. This FPGA was designed on the basis of homogeneous 3D-stacking to extend the logic scale in proportion to the number of stacked layers. To improve Z-axis transmission performance, a wafer-to-wafer stacking process for lowering the capacitance of TSV was developed. An “embedded TSV“ design for the shorter on-chip wirings was also devised. Moreover,...
A wafer-level three-dimensional (3D) integration scheme for forming via-last through-silicon vias (TSVs) was developed. This scheme includes wafer-to-wafer (W2W) stacking technology with a copper/polymer hybrid bonding and a via-last TSV process compatible with a copper/low-k interconnect structure. Bonding of a copper/polymer hybrid wafer with a ventilation channel structure provides good copper-to-copper...
Successful 3D integration of a stacked chip fabricated by a “chip-level through-silicon-via (TSV)” process was confirmed by inter-chip data transmission. According to measurements of the electrical properties of the stacked chip, structural design of TSV contact wiring is very important for chip-level/via-last TSV integration. That is, the design influences TSV contact resistance, TSV coupling capacitance,...
We describe a Through Silicon Via (TSV) interconnect for multi-layer stacked chips by using a low capacitance TSV and by introducing a novel circuit design with an adaptive timing control. Studying effects of TSV parasitic capacitances on the interconnect performance, a low capacitance TSV was designed and was experimentally confirmed that the capacitance was 90 fF/TSV. To enhance the performance,...
For rapid prototyping of system LSIs based on three-dimension (3D) integration using through-silicon-vias (TSVs), a TSV fabrication technology for a diced chip with copper/low-k interconnections (called “chip-level TSV integration”) was developed. The two key processes of this technology are uniform substrate thinning in chip form and via-last TSV formation for nanometer-sized copper/low-k interconnection...
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