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Hybrid bonding, with wafer-level bonding to form oxide-oxide bonds and Cu-Cu bonds, is a promising technology for 3D integrated circuits. In this study, we describe the design, processing. and characterization of test structures formed using hybrid bonding for wafers built in two different technologies; a 180 nm Al BEOL technology and a 110nm Cu BEOL technology. The reliability evaluation shows good...
Two unique gate oxide failure mechanisms are associated with deep trench processes for a 0.18 μm power semiconductor device. One failure mode is a “mini-LOCOS” defect, that is due to inadvertent oxidation of Si in the active area during deep trench oxidation. The other failure mode is due to slip associated with dislocations from the deep trenches. These defects are eliminated by optimizing the SiN...
X-Ray Diffraction Imaging (XRDI) is used to non-destructively image strain in Si associated with deep trench isolation in high voltage devices. The XRD images show that there is dark contrast associated with deep trenches which is indicative of strain and defects in a material. Using defect etching, it is shown that there is a tendency for higher dislocation densities in regions where there is dark...
X-Ray computed tomography (CT) can be useful in evaluating defects in through-silicon vias (TSVs). X-Ray CT images of two different TSV processes are presented; copper TSVs used for stacked memory on logic and tungsten TSVs used for power amplifiers. It is found that TSVs in the edge exclusion region are susceptible to defects from the TSV etch and TSV metallization processes.
Through-silicon-via (TSV) technology is conceptually simple, but there are many process control issues in volume manufacturing. An important parameter is TSV depth, because the product yield will be reduced if TSV depth is either too shallow or too deep. Recently, it has been shown that TSV depth can be measured using an interferometric sensor operated at infrared (IR) wavelengths. In this paper,...
The reliability of circuits (wiring and vias) under bond pads has been studied for both Au wire bonding and Cu wire bonding, for bond pads and wiring levels typical of those used in RF technology. Electrical test structures under bond pads were used to characterize wire and via integrity after wire bonding and reliability stresses. In addition, SEM analysis was used to inspect for possible damage...
On-chip copper interconnects have gained wide acceptance in the microelectronics industry due to improved resistivity and reliability compared to Al interconnects. Initially, copper interconnects were only used for high performance logic circuits. However, Cu interconnects are now used in a wide variety of integrated circuits, including dynamic random access memories (DRAM), RF circuits, and CMOS...
As device dimensions and wire dimensions are reduced, it is desirable to increase the electromigration lifetime of Cu. A simple method to improve the electromigration lifetime is to dope the Cu with impurities, such as Al, Ag, Ti, or Mn, using an alloy seed layer. During subsequent anneals, the impurities segregate at grain boundaries and interfaces, including the critical interface between the Cu...
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