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A fast design space exploration of analog firm intellectual properties (IP) based on Peano-like paths (piecewise linear and monodimensional) is presented. First, the n-dimensional design space is globally explored following those Peano curves, which are obtained by varying only 1 design variable at a time using a fixed step size. Each variable is taken within a given range. During exploration, the...
This paper presents a structured DC analysis methodology for analog circuit verification. The electrical simulator, usually executed to perform verification, is here replaced by a nonlinear DC solver based on the analysis bipartite graph. The analysis bipartite graph, associated to a circuit, is a formal representation of the circuit DC behavior. Thus, the analysis bipartite graph evaluation provides...
This paper presents an algorithm, based on the fixed point iteration, to solve for sizes and biases using transistor compact models such as BSIM3v3, BSIM4, PSP and EKV. The proposed algorithm simplifies the implementation of sizing and biasing operators. Sizing and biasing operators were originally proposed in the hierarchical sizing and biasing methodology [1]. They allow to compute transistors sizes...
This paper presents a unified platform for design and verification of mixed-signal systems based on the SystemC AMS standard. The platform relies on a top-down design methodology. In this methodology, several hierarchical abstraction views of the system are considered. These abstraction levels are: system, functional, macromodel and circuit levels. We introduce a simple and efficient method to implement...
This paper presents a methodology for procedural layout-aware design for nanometric technologies. A Python-based layout generation tool generates different layout styles for the same basic analog building blocks. Moreover, layout dependent parasitic parameters such as stress effects are easily computed and compared for different layout styles. The procedural layout description is written using a Python...
This paper presents a new formalization of a hierarchical methodology for the sizing and biasing of analog IPs using bipartite directed acyclic graphs. This methodology allows to generate suitable sizing procedures that respect designer hypothesis and circuit topology. A library of simulator-based sizing and biasing operators using compact MOS models is used to ensure accurate sizing over different...
In this paper, a new method for developing smart parameterized generators for analogue devices is presented. A device is an atomic analogue cell that performs an elementary and standard function such as the differential pair and the current mirror. A device is smart since it can be electrically and physically adapted. In the proposed method, the device sizes and biases are first computed using dedicated...
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