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In this paper, we propose a Membership function Generator (MFG) circuit in the form of Gaussian and trapezoidal for Neuro-fuzzy applications which is programmed by four voltage signals. Two signals define the knees where output signals begin falling or rising, while other ones change the rising or falling slopes of Gaussian and trapezoidal functions, independently. So there is no need to change the...
In carry-select adders (CSAs), using a single ripple carry adder and a first zero finder (FZF) circuit instead of dual ripple carry adder has an impressive impact on reduction of number of transistors and so power consumption of adder. On the other hand, combination of CSA and carry-lookahead adder (CLA) improves speed of this adder. In this paper a 64-bit static adder with structure of a hybrid CLA/CSA...
This paper presents a high-speed 16×16-bit CMOS pipelined booth multiplier. By using new partial product generation and booth encoder circuits and a novel adder, speed of pipelined multipliers is improved. By these new architectures, final adder performs 25 bit addition in only two cycles with high speed (1.6 GHz). Due to lower number of cycles (5 clock cycles), delay of the overall circuit is only...
This paper presents a high-speed 16×16-bit CMOS pipelined booth multiplier. By using new partial product generation and booth encoder circuits and a novel adder, speed of pipelined multipliers is improved. By these new architectures, final adder performs 25 bit addition in only two cycles with high speed (1.6 GHz). Due to lower number of cycles (5 clock cycles), delay of the overall circuit is only...
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