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Interconnections are increasingly the dominant contributor to delay, area and energy consumption in CMOS digital circuits. Multiple-valued logic can decrease the average power required for level transitions and reduces the number of required interconnections, hence also reducing the impact of interconnections on overall energy consumption. In this paper, we propose a quaternary lookup table (LUT)...
Analog designers are challenged by increasingly complex device models and lowered signal swing as the CMOS processes scale. At the same time, new trends and emerging technologies pose tighter design constraints. However, the cheap computational resources nowadays enable the use of the mature electrical simulators and device models in simulation-in-a-loop optimization techniques. In this work, we present...
This paper describes the implementation of an IR-UWB transmitter using an oscillator, and where the pulse duration is controlled digitally by the oscillator frequency. In this new topology, the consumption is reduced to the leakage current when it is not producing a pulse, ensuring high power efficiency even for low data rates. The proposed circuit is inductorless and implemented in a standard UMC...
A novel differential output track and hold (TH) circuit with configurable common-mode output voltage is presented. Its structure avoids the coupling circuits required when dealing with different common-mode levels in differential signals. Another novelty of the proposed design is its ability to track single-ended signals, and convert the output to a steady differential voltage, with a programmable...
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