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In this paper, we present a design time tool, EASTA, that combines reconfigurability in FPGAs and Dynamic Frequency Scaling to realize an efficient multiprocessing architecture on a single-FPGA system. Multiple deadlines, re-convergent nodes, flow dependency and processor constraints of the multi-processor problem on a general task graph are rigorously taken into consideration. EASTA is able to determine...
On 16 December 2015, the National University of Singapore (NUS) launched two of its first small satellites - the 80kg class micro-satellite Kent Ridge-1, and the 2U CubeSat Galassia, into space. The event marked a milestone in the history of Singapores nascent space industry. Regulatory requirements of the country mandate that pre-launch and post-launch casualty risk assessments be performed in the...
The use of reverse body bias (RBB) in circuit design is recognized to be a viable strategy for managing leakage power, a burning issue as process nodes continue to shrink beyond the 20nm realm. This technique is especially useful to FP-GAs, which are able to tune RBB modes on-the-fly, offering leakage power reduction with very little impact to circuit speed. Most works today on RBB as applied to FPGAs...
In this paper, we present a technology mapping and clustering tool for leakage power reduction in FPGAs with programmable, dual-VT logic blocks. The use of Reverse Back Bias (RBB) circuit techniques is recognized as one of the more promising strategies in mitigating leakage power, a critical problem in circuits deploying deep submicron process technologies. FPGAs with the ability to adjust fabric...
Process variations of deep sub-micron technologies have created significant timing uncertainty. This generates the need for a new variability-aware physical synthesis tool for Field-Programmable Gate-Arrays (FPGAs). Ideally, variability-aware tools should be able to perform both timing variability estimation during the synthesis and timing variability analysis after the synthesis. Statistical static...
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