The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In addressing the problem of area overhead, physical routing and timing management between memory built-in self-tests (MBISTs) controllers with hundreds of embedded memories in system on Chip (SoC), various approaches have been proposed. In addressing these problems, MBISTs structure and architectural design should be efficiently determined in detail so that the problems associated with the issues...
Integrating a large number of embedded memories in System-on-Chips (SoC's) occupies up to more than 70% of the die size, thus requiring Built-In Self-Test (BIST) with the smallest possible area overhead. This paper analyzes MATS++(6N), March C-(10N), March SR(14N), and March CL(12N) test algorithms and shows that they cannot detect either Write Disturb Faults (WDFs) or Deceptive Read Destructive Faults...
This work proposes a bit-adjacent Data Background (DB) management scheme to improve fault coverage of March algorithms while simultaneously maintaining the shortest test cycle. Both static and dynamic DB transitions are used in order to detect Deceptive Read Destructive Faults (DRDFs) and Write Disturb Faults (WDFs) that are not detected by previous algorithms. A conventional March Test Algorithm...
At-speed scan testing for intra-clock and inter-clock transition delay faults in a SOC design with multiple clock domains is an important and challenging issue. Current practice in industry usually applies a test scheme targeted on intra-clock transition fault delay testing (i.e., intra testing). In this paper a test scheme targeting both intra-clock and inter-clock domains for transition delay fault...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.