Search results for: Takashi Takemoto
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A 56-Gb/s optical receiver, consisting of a PD and a SiGe BiCMOS TIA flip-chip mounted on a ceramic package, was developed. It achieves error-free operation (at 56 Gb/s) with jitter margin of 0.38 UI.
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A 50.6-Gb/s optical receiver (RX) based on the 0.18-µm SiGe BiCMOS technology was fabricated and evaluated. To improve phase margin and sensitivity of the RX without degrading its power efficiency, it was configured with a two-stage pre-amplifier (preamp) with high gain (56 dBΩ) and power-supply-variation (PSV) canceller for improving sensitivity. The RX achieves sensitivity of −7.4 dBm and phase...
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Reproductive Biology and Endocrinology > 2016 > 14 > 1 > 1-7
Background Patients hoping to preserve their fertility receive conservative treatment with high-dose medroxyprogesterone acetate (MPA) for well-differentiated endometrioid adenocarcinoma (EC) or atypical endometrial hyperplasia (AEH) . Such treatment generally involves frequent intrauterine operations, including dilation and curettage (D&C) and endometrial biopsy (EMB), which could result in endometritis,...
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Journal of Lightwave Technology > 2015 > 33 > 23 > 4891 - 4898
Jitter of a 25-Gb/s optical link is numerically and experimentally analyzed. The numerical analysis shows that a 25-Gb/s optical transceiver needs retiming circuits in its transmitter and receiver in order to satisfy the targeted jitter budget of the optical link. Because the random jitter (RJ) largely contributes the total jitter of the 25-Gb/s optical link, an equation for calculating the RJ caused...
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An electrical and optical concurrent design methodology for enlarging the jitter margin of 25.8-Gb/s optical interconnects is proposed and evaluated. As the key for establishing this design methodology, a simple method for modeling characteristics of a laser diode (LD) (hereafter, "LD modeling method") is adopted. The LD modeling method calculates an optical eye diagram on the basis of measured...
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A 103.2 (25.8 × 4)-Gb/s optical link using a 1.3-µm lens-integrated surface-emitting laser array was demonstrated. A power penalty after 2-km transmission was small (<1dB) at 25°C. Moreover, error-free transmission up to 70°C was achieved.
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A 50-Gb/s optical transmitter, consisting of a DFB-LD with a bandwidth of 20 GHz and a SiGe BiCMOS LD driver, was developed. At 43-50 Gb/s, it enhanced a LD bandwidth and demonstrated wide eye openings.
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This paper describes the design and experiment results of 25 Gbps, 4 channels optical transmitter which consist of a vertical-cavity surface emitting laser (VCSEL) driver with an asymmetric pre-emphasis circuit and an electrical receiver. To make data transfers faster in directly modulated a VCSEL-based optical communications, the driver circuit requires an asymmetric pre-emphasis signal to compensate...
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IEEE Journal of Solid-State Circuits > 2014 > 49 > 2 > 471 - 485
A one-chip optical transceiver for board-to-board transmission was developed by integrating an analog frontend (FE) with a data-format-conversion (DFC) block in 65-nm CMOS process technology. It was experimentally demonstrated that this transceiver can convert 10x 6.25-Gb/s electrical signals to 4x 25-Gb/s optical signals with 25% redundancy that improves resilience against possible laser diode (LD)...
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IEEE Journal of Solid-State Circuits > 2014 > 49 > 10 > 2259 - 2276
To address the two main challenges concerning the design of a transimpedance amplifier (TIA), namely, improving the sensitivity of the TIA without sacrificing bandwidth and suppressing inter-symbol interference (ISI) due to insertion loss, a 25 Gb/s optical receiver (RX) based on 65 nm CMOS technology, including a TIA and a PD operating at 1.3 wavelength, was developed. The key components...
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A 25 Gb/s × 4-ch, 8 × 8 mm2 optical transceiver module for optical interconnection has been developed. To obtain a compact optical module suitable for chip-to-chip interconnection, a lens integrated connector, a small low temperature co-fired ceramic (LTCC) package, and a precise lens assembling technology were used. Experimental results showed that the proposed module can achieve 25 Gb/s error free...
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Growing data traffic requires low-power 25Gb/s-class optical interconnects for board-to-board transmission inside ICT systems [1–4]. The main power consumption of an optical link strongly depends on the sensitivity of the TIA; thus, development of a high-sensitivity TIA is a key to creating a low-power optical link., There are two challenges concerning the design of such a TIA: (1) improving the sensitivity...
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A 25-Gb/s optical transceiver module has been developed for backplanes. An optical transceiver for backplanes is necessary to downsize current modules while reducing power consumption and increasing speed up to 25 Gb/s. We employed many approaches to achieve this by reducing crosstalk noise, by enhancing power integrity, and by using CMOS-based analog FE and on-chip termination and optical waveform...
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A high-stability and high-speed optical transceiver module for a chip-to-chip optical interconnection has been developed. The stability of optical power output is provided by optimizing the packaging structure snd thus reducing deformation of the module resulting from the bimetallic effect. (Degradation of optical coupling efficiency is reduced to 0.15dB by limiting variations in temperature to a...
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A hybrid integration of a surface emitting DFB lasers and a fully integrated transceiver CMOS chip was proposed for compact 100-Gb/s transceivers of optical backplanes and datacenter optical links.
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A one-chip transceiver was developed for optical backplanes by integrating an analog FE with data format conversion in 65-nm CMOS. 10×6.25Gb/s electrical signals were converted to 4×25Gb/s optical signals with 25% redundancy to improve resilience against possible LD failure. To alleviate degradation of the optical link due to power-supply variations, a TIA with a noise canceller and a fully differential...
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A compact optical low-power (9 mW/Gbps) transceiver with lens integrated devices and 12-ch flexible waveguides for optical interconnects was developed. It provides high optical-coupling efficiency and large tolerances (>-2.5 dB and >+/-15 μm) and demonstrated 25-Gbps/ch error-free transmission.
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IEEE Photonics Technology Letters > 2012 > 24 > 6 > 467 - 469
A prototype transceiver composed of a 1.3--range lens-integrated laser diode and photodiode as well as a complementary metal–oxide–semiconductor (CMOS) laser diode driver and a CMOS transimpedance amplifier for high-speed optical interconnections was developed. It demonstrated 25-Gb/s error-free 100-m multimode fiber transmission, with power dissipation of only 9 mW/Gb/s, for the first time.
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The world's first CMOS "gearbox LSI" based on 65-nm CMOS technology-namely, a 2-W 100-gigabit-Ethernet gearbox LSI combining a 10:4 multiplexer and a 4:10 demultiplexer-was developed. Its power consumption is 75% lower than that of a conventional SiGe-based gearbox LSI. The power consumption of its 12.5-Gb/s interface is 0.98 mW/(Gb/s), while that of its 25- Gb/s interface is 14 mW/(Gb/s).
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A compact 25-Gbps × 4-channel optical transceiver has been fabricated for optical backplane systems. Power consumption was as low as 20 mW/Gbps. A transmission experiment was successfully conducted at 25 Gbps.
