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Systems with more and more sophisticated self-management capabilities are introduced in many application domains, such as robotics, the military, aerospace, ground vehicles, IT network and systems management. So far, descriptions of such systems are neither decomposed into common modules nor aligned to a common reference model. For this reason, it is hard to compare them regarding common cross-domain...
The mapping process of high performance embedded applications to today's reconfigurable multiprocessor System-on-Chip devices suffers from a complex toolchain and programming process. Thus, the efficient programming of such architectures in terms of achievable performance and power consumption is limited to experts only. Enabling them to nonexperts requires a simplified programming process that hides...
Reconfigurable tile-based architectures can dynamically interconnect several tiles in order to establish processor instances with varying resource, performance, and energy characteristics at run time. These flexible processor instances offer a new degree of freedom for adapting to changing applications' requirements while optimizing resource and energy consumption. Our solution for dynamic interconnection...
The sustained advance in technology will enable integrating hundreds of processing cores on a single die in near future. However, it already can be foreseen that the management of the resources of such large systems will not scale in the same way as the hardware using todays entirely software based and centralized management approaches. The invasive paradigm addresses this problem and proposes concepts...
Processor architectures that are capable to reconfigure their instruction set and instruction format dynamically at run time offer a new flexibility exploiting instruction level parallelism vs. thread level parallelism. Based on the characteristics of an application or thread the instruction set architecture (ISA) can be adapted to increase performance or reduce resource/power consumption. To benefit...
Reconfigurable processor architectures can dynamically switch their instruction set and instruction format at run time. They offer a new flexibility for adapting to changing applications' requirements in order to optimize performance and enable resource-awareness. While programmability is a key issue of such architectures, today's software toolchains are limited to static ISA architectures and must...
Reconfigurable chip multiprocessors realizing very long instruction word (VLIW) processors of dynamically-scalable issue width enable resource-aware adaptation to diverse processing requirements. The execution performance of such clustered VLIW processors is significantly influenced by different design parameters of the fundamental processing cores. In this paper we present a design space exploration...
The dynamic run-time complexity of embedded applications is steadily increasing. Currently, only specialized Multiprocessor System-on-Chip (MPSoC) architectures can deliver the required processing power as well as energy efficiency. Although today's MPSoCs incorporate different, potentially reconfigurable cores, their ability to dynamically balance exploitable instruction-, data-, and thread-level...
Facing the requirements of next generation applications, current approaches of embedded systems design will soon hit the limit where they may no longer perform efficiently. The unpredictable nature and diverse processing behavior of future applications requires to transgress the barrier of tailor-made, application-/domain-specific embedded system designs. As a consequence, next generation architectures...
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