The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Performance variation is one of the primary concerns in nanometer-scale dynamic CMOS circuits. This performance variation is worse in circuits with multiple timing paths such as those used in microprocessors. In this paper, a Process Variation-aware Transistor (PVT) sizing algorithm is proposed, which is capable of significantly reducing worst-case delay, delay uncertainty, and delay sensitivity to...
This paper describes an RFID and GPS integrated navigation system, Smart-Robot (SR) for the visually impaired. The SR uses RFID and GPS based localization while operating indoor and outdoor respectively. The portable terminal unit is an embedded system equipped with an RFID reader, GPS, and analog compass as input devices to obtain location and orientation. The SR can guide the user to a predefined...
The advancement in CMOS technology with the shrinking device size towards 32 nm has allowed for placement of billions of transistor on a single microprocessor chip. Simultaneously, it reduced the logic gate delays to the order of pico seconds. However, these low delays and shrinking device sizes have presented design engineers with two major challenges: timing optimization at high frequencies, and...
The complexity of timing optimization has been increasing rapidly in proportion to the shrinking CMOS device size, due to the increased number of channel-connected transistors in a path, and the rising magnitude of process variations. These significant challenges can be addressed through the implementation of designs with an optimal balance between static and dynamic circuits. This paper presents...
A major challenge in the design of microprocessor circuits is transistor sizing in dynamic CMOS logic due to increased number of channel-connected transistors on various paths of the design, and increased magnitude of process variations in the nanometer process. This paper proposes a process variation aware transistor sizing algorithm for dynamic CMOS logic. The efficiency of this algorithm is illustrated...
Due to the increased importance of speed on microprocessor circuits, the complexity in transistor sizing for timing optimization increases due to channel-connected transistors on various paths of the design. In this paper, an efficient approach to transistor sizing of dynamic CMOS circuits for timing optimization while considering the load balance of multiple paths, named LBMP, is proposed. The iterative...
This paper presents a low-cost low-power self-test design and verification of on-chip analog-to-digital converter (ADC) for system-on-a-chip (SoC) applications. A methodology for performing mixed-mode built-in self-test (BIST) simulation was performed along with the BIST architecture. The architecture presented allows for generation of analog test signals of frequency up to 600 MHz, using a 4-b 2...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.