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Presented is a soft-decision decoding algorithm for a particular class of rate-1/2 systematic linear block codes. The proposed algorithm performs successive re-encoding of both the data and parity bits, to produce a list of codewords among which the most likely candidate is chosen. Simulation results show that close to optimal performance can be obtained at reasonable complexity. They validate the...
Cortex codes are a family of rate-1/2 self-dual systematic linear block codes with good distance properties. This paper investigates the challenging issue of designing an efficient soft-decision decoder for Cortex codes. A dedicated algorithm is introduced that takes advantage of the particular structure of the code to simplify the decoding. Simulation results show that the proposed algorithm achieves...
This article presents an innovative turbo product code (TPC) decoder architecture without any interleaving resource. This architecture includes a full-parallel SISO decoder able to process n symbols in one clock period. Syntheses show the better efficiency of such an architecture compared with existing previous solutions. Considering a 6-iteration turbo decoder of a (32,26)2 BCH product code, synthetized...
In this paper, the use of single-error-correcting Reed-Solomon (RS) product codes are investigated in an ultra high-speed context. A full-parallel architecture dedicated to the turbo decoding process of RS product codes is described. An experimental setup composed of a Dinigroup board that includes six Xilinx Virtex-5 LX330 FPGAs is employed. Thus, a full-parallel turbo decoding architecture dedicated...
In this paper, we demonstrate the higher hardware efficiency of Reed-Solomon (RS) parallel turbo decoding compared with BCH parallel turbo decoding. Based on an innovative architecture, this is the first implementation of fully parallel RS turbo decoder. A performance analysis is performed showing that RS block turbo codes (RS-BTC) have decoding performance equivalent to Bose Ray-Chaudhuri Hocquenghem-block...
We study the minimum distance of the binary expansion of high-rate Reed-Solomon (RS) codes and product codes in the polynomial basis and show that the binary codes obtained in this way usually have minimum distance equal to the designed symbol minimum distance. We then show that a judicious choice for the code roots may yield binary expansions with larger binary minimum distance and better asymptotic...
In this paper, the first flexible architecture dedicated to block turbo decoders is presented The major innovation concerns the component code that is used by the block turbo code. In fact, our architecture is able to decode BCH and Reed-Solomon codes with single or double correction power. To the authors' knowledge, this is the first architecture implementing Reed-Solomon block turbo codes. This...
Reed-Solomon codes are block-based error correcting codes with a wide range of applications in digital communications and storage. Recently, block turbo codes using Reed-Solomon component codes have been introduced. This was motivated by the highest code rate property of Reed-Solomon codes and their efficiency for burst error correction. In fact, the main advantage of Reed-Solomon block turbo codes...
More than ten years after their introduction, turbo Codes are now a mature technology that has been rapidly adopted for application in many commercial transmissions systems. This paper provides an overview of the basic concepts employed in convolutional and block turbo codes, and review the major evolutions in the field with an emphasis on practical issues such as implementation complexity and high-rate...
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