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We reported a wafer level through-stack-via (TSV) integration approach for stacked memory module using onetime bottom-up copper filling. This bumpless TSV integration approach simplified the fabrication process and provided better reliability compared with solder based technologies. Silicon wafer with blind vias was first bonded to a carrier wafer face to face with pre-patterned BCB, and then thinned...
In this study, a stacked SRAM module with a built-in decoder was proposed with a through-multilayer TSV integration process. The through-multilayer TSVs provided data passages for all common signals, including the address bus, data bus, power, read and write control, which were redistributed at each individual chip, while the chip select signals were connected separately to the built-in decoder. Regarding...
In this paper, a novel 3D integration process named Via-Backside-Release process, abbreviated as VBR process, is proposed and technical issues are addressed. With VBR process, there's no need of removal process of copper overburden due to the filling of TSV by copper electroplating, and no individual unit process for producing Cu/Sn microbumps. In order to verify the feasibility of VBR process, a...
3D integration with TSVs is emerging as a promising technology for the next generation integrated circuits. TSV filling is a critical process in TSV fabrication and has direct effect on electrical performance of TSVs. In this paper, we mainly focus on effect of additives used in methanesulfonic based solution on copper electroplating filling. Numerical simulation based on an absorption-diffusion model...
In this paper, a stacked SRAM chip module is presented and simulation results are demonstrated. A novel 3D integration process is presented and challenging issues are addressed. With this novel process, there's no need to do grinding/polishing of copper overburden after filling of TSV by copper electroplating. Copper microbumps will be formed directly on the active side in the filling of TSV by copper...
In this paper, a process for making copper Though-Silicon-Via (TSV) interconnection is developed. In order to improve the yield of the process, challenging issues in the process is discussed and typical failures in the TSV interconnection are summarized. A measuring scheme is proposed to monitor these failures in the process and simulation is performed to testify the feasibility of the method.
In this paper, we present our recent advances in streamlining via-last TSV process flow. Parylene deposition, which is of excellent conformability to the substrate landscape, was introduced into TSV blind via filling process to realize uniform sidewall protection. Simulation was made to analyze the impacts of parylene sidewall on the electric field distribution inside a blind via with high aspect...
This paper reports the designing/simulation and experimental investigation into the Deep RIE-based micro-fabrication of through-Si-via (TSV) which acts as the vital vertical interconnect for compact 3-D system-in-package integration. An in-house developed process simulator based on cell/string evolution algorithm and physical modeling is used to explore suitable DRIE conditions for drilling vias with...
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