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Despite the fact, that Sweden has one of the safest traffic environments in the world, a large number of people are still injured in road traffic accidents in Sweden. The core concept of the Vision Zero that was adopted by the Swedish parliament in 1997 is to decrease the number of deaths and serious injuries caused by traffic. The vision has been followed-up in terms of decreased mortality, but there...
In this paper we propose a differential dynamic dual rail CMOS logic style for ultra-low-voltage and high-speed operation. For a supply voltage equal to 300mV using a 90nm TSMC CMOS process the delay of the proposed logic style is reduced more than 96% compared to the delay of dual rail clocked voltage switch logic.
The Ultra Low-Voltage (ULV) NAND and NOR gates are presented in this paper. These gates are based on the ULV precharge inverter presented in [11]. We intend to verify the gates' logical expression of NAND and NOR. The inbound precharge logical behaviours of the gate have been previously discussed, and therefore we aim to compare these new NAND and NOR designs to traditional Domino and CMOS logic styles...
In this paper we improve the Ultra Low-Voltage gate by including a keeper transistor at the floating-gate to make the gate more static. Thus, the refresh overhead is excluded, in addition the power consumption in evaluation period is significant lower. We also evaluate the gates behaviour for the effect of delayed input signal. All results are obtained by simulation in Cadence for a 90 nm process...
In this paper we present high-speed and ultra low-voltage pass transistor. The delay of the proposed pass transistors are less than 6% of conventional CMOS pass transistors operating at supply voltages down to 200mV. The pass transistor logic presented can be used to implement low-voltage high-speed serial adders. The simulated data provided is obtained using Cadence and 90nm TSMC CMOS process.
In this paper we present a novel differential CMOS D Flip-Flop based on a high-current pass transistor. We use floating capacitors to obtain a current boost at specific events, i.e clock edges. The Flip-Flop presented may be used inany low voltage digital CMOS systems. The delay is reduced to approximately 12% compared to a conventional sense. amplifier differential Flip-Flop. The simulated data provided...
In this paper we present novel high speed and ultra low voltage domino invererters. The delay of the inverters are less than 4% of the delay for a standard CMOS inverter. A low power inverter is included and the simulated data for supply voltages in the range of 200mV to 400mV are provoded. Monte carlo simulation show that the ULV logic styles are less influenced by process mismatches than standard...
In this paper we present a novel CMOS pass transistor logic style for ultra low-voltage and high speed digital applications. The circuits presented offer more than 90% delay reduction compared to conventional CMOS for supply voltages less than 400mV. Differential AND and NAND pass transistor gates presented and compared to complementary pass transistor logic CPL. Simulated data obtained by the H spice...
In this paper we explore volatile floating-gate CMOS circuits aimed for ultra-low analog design. The analog transconductance amplifier presented may operate down to 250mV in a STM 90nm CMOS process with an inherent threshold voltage of 270mV. The ultra-low transconductance amplifier has a current boost function and resembles switch-cap and auto-zero circuits. The ultra-low voltage analog circuits...
In this paper we present a novel ultra-low-voltage (ULV) CMOS flip-flop. The ULV flip-flop offers increased speed compared to other FF's for low supply voltages. The pulse generator (PG) circuit in a conventional sense amplifier SAFF is replaced by a high-speed tristate edge generator (EG) with a rise- and fall-time less than 1/10 of an inverter operating with the same supply voltage. In essence the...
In this paper we present a novel high speed and ultra low-voltage full adder circuit based on ultra low-voltage semi floating-gate CMOS logic. The full adder circuit contains a high speed ultraslow-voltage carry generator circuit and a multiple-valued intermediate representation of the summation. The full adder is suitable for low-voltage serial full adder design. Simulated data presented is valid...
In this paper we present novel ultra-low-voltage (ULV) CMOS flip-flops (FF). The FFs offer increased speed compared to conventional CMOS FF for ultra low supply voltages. ULV logic FFs can be operated at a clock frequency more than 10 times than the maximum clock frequency of more conventional CMOS FFs for ultra low supply voltages. The simulated data presented is obtained using the Spectre simulator...
In this paper we explore the bi-directionality of pseudo floating gate analog circuits. The basic pseudo floating-gate current starved inverter is symmetric with respect to the supply rail, and the signal flow can be altered by flipping the supply rails. Different circuits configurations, including a differential to single-ended amplifier, single-ended to differential amplifier, follower integrator...
In this paper the effects of process variations on SRAM cell are investigated. The SNM (static noise margin) changes due to the threshold voltage variations, is discussed in details. In addition, the effect of NBTI in sub-threshold SRAM design is presented. Simulation results shows the effect of process variation including mismatches on SRAM cell. The SNM is degraded by 35% for higher temperatures...
In this paper we propose a novel ultra low-voltage and high speed domino CMOS logic style. The proposed logic style utilizes floating-gate transistors which are used to increase the current level of the transistors driving the output of the gates. In this way the delay of the proposed logic style may be reduced to less than 10% compared to standard CMOS.
In this paper we present a novel ultra-low-voltage (ULV) CMOS flip-flop (FF) exploiting ULV semi-floating CMOS logic. The ULV gates applied offer increased speed compared to other CMOS logic styles for low supply voltages. ULV logic gates can be operated at a clock frequency more than 10 times than the maximum clock frequency of a similar complementary CMOS gate operating at the same supply voltage...
In this paper we present timing details for static ultra-low-voltage (ULV) CMOS inverters and latches. The logic presented resemble domino CMOS logic and is more than 10 times as fast as complementary CMOS for very low supply voltages. Static ULV inverters and latches are presented and preliminary simulated data are provided for a 90nm TSMC CMOS process.
In this paper we explore symmetric floating-gate CMOS circuits aimed for ultra-low analog design. The analog transconductance amplifier presented may operate down to 250mV in a STM 90nm CMOS process with an inherent threshold voltage of 270mV. The ultra-low transconductance amplifier has a current boost function and resembles switch-cap and auto-zero circuits. The current boost technique have been...
In this paper we present an ultra low-voltage static CMOS carry generate circuit. The circuit may operate at supply voltages below the inherent threshold voltage of the transistors while maintaining a current level of transistors operating in strong inversion. The circuit show an improved performance compared to standard CMOS in terms of delay. Preliminary results indicate a reduced delay to approximately...
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