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In order to obtain power efficient flip-flops, two novel Hybrid-latch schemes are introduced in this paper. They achieve high performance by shortening the critical data path and power efficiency by eliminating the inverter chain pulse generator. HSPCE simulation under SMIC 90nm process revealed that the two new flip-flop have excellent power and speed performance compared to the referenced design...
RapidIO is a high-performance standard for embedded interconnections. Due to different ending alignments of RapidIO packets, the corresponding CRC computations should be adjustable. In this paper, two selective parallel computation schemes based on simplified intermediate value equations are proposed. Compared with the reference designs, the power dissipations can be reduced by more than 30% meanwhile...
RapidIO is a high performance open standard for the next-generation embedded interconnection technology. In this paper, an improved pivotal buffer core which plays a crucial role in the RapidIO packet transmission is described in detail. It uses the four-isolated-queue as the outbound framework for better quality of service and a certain amount of blocks with sharing and binding attempts mechanism...
RapidIO is an attractive interconnection technology due to its high performance and high reliability. In this paper, the design of serial physical layer in 4x mode with 64-bit inner bus is described in detail. It achieves the goals of link transmission, flow control, error detection and recovery. It is considered to be a feasible and reliable part of SRIO in the high speed embedded system interconnection.
RapidIO is an emerging high-performance and point-to-point packetized interconnection technology. In this paper, the design of the logical core based on safety arbitration mechanisms is described in detail. The packing and unpacking of I/O Logical, Message Passing and Globally Shared Memory transactions are achieved. Excellent average data transfer rates, up to 7.8 bytes per cycle are reached in certain...
In this paper, we propose multi-node driving circuits for multi-branch transmission wires. Power dissipation could be decreased remarkably by dividing the full signal swing into several low swings through charge redistribution. HSPICE simulations show that while driving three branches with load capacitance of 1 pF each, the proposed scheme can save the power by more than 66% compared with the circuit...
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