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This paper addresses the problem of logic diagnosis of System-on-Chip (SoC). We propose a diagnosis approach based on a matching algorithm between a set of predicted failures and the set of failures observed during the test phase. The result of the diagnosis is a ranked list of suspected nets able to explain the observed failures. Experimental results show the diagnosis accuracy of the proposed approach...
The importance of delay faults proportionally increases when entering in the nano-technology era, and logic diagnosis must localize delay faults as precisely as possible to speed-up yield ramp-up. This paper presents a logic diagnosis approach targeting delay faults. The proposed approach is based on the single-location-at-a-time (SLAT) paradigm used to determine a set of suspects. It addresses the...
This paper presents a diagnosis method targeting System-On-Chip (SoC). We first show the complexity and the issues related to the diagnosis of SoC. Then we propose a diagnosis approach based on fault simulation performed in two phases, (i) a fault localization phase and (ii) a fault model allocation phase. The fault localization phase peovides a set of suspected lines able to explain the observed...
This paper presents a logic diagnosis approach performed in two phases, (i) a fault localization phase searching in to the dictionary a set of suspected lines able to explain the observed errors, and (ii) a fault model allocation phase associating a set of fault models on each suspect identified in the first phase. The main advantages of this approach are that the fault localization phase is fault...
This paper presents a logic diagnosis approach targeting bridging faults. The proposed approach is performed in two phases, (i) a fault localization phase based on the single-location-at-a-time (SLAT) paradigm determining a set of suspects, and (ii) a fault model allocation phase associating a set of fault models to each suspect identified during the first phase. The main advantages of this approach...
This paper presents an industrial case study on logic diagnosis targeting system-on-chip (SoC). We first show the complexity and the issues related to the diagnosis of SoC. Then we propose a diagnosis approach based on the effect-cause paradigm. This approach consists of two phases: (i) a fault localization phase resorting to the critical path tracing to determine a set of suspects, (ii) a fault model...
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