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Using experimental and numerical simulation analysis the breakdown voltage walkout effect has been studied in 40 V ESD protection devices based on extended drain MOS devices implemented in a 5 V CMOS process. A similar effect has been observed in 100 V and 24 V BiCMOS processes. The physical mechanism of this effect is revealed as the result of hot electron capture in the thick field oxide of the...
A new high holding voltage lateral PNP device is experimentally demonstrated in a 40 V drain-extended CMOS process, followed by a new compact PNP-SCR device-level solution utilizing a two-stage snapback. The advantage of these lateral DeMOS-based devices is the capability to provide local ESD protection that is robust against transient latch-up for pins with system level, hot swap, and hot plug-in...
A new high voltage lateral PNP with sufficient current density for small footprint ESD protection is experimentally demonstrated in a 40 V drain-extended CMOS process. It is found that a lateral PNP device can exhibit snapback behavior similar to that characteristically associated with NPN-based ESD clamps. The mechanism leading to this effect is further studied for PNPs in a BiCMOS process using...
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