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This paper studies for the first time the low temperature characteristics of strained SOI FinFETs submitted to proton irradiation. Both types of transistors, nMOS and pMOS, were analyzed from room temperature down to 100K, focusing on the threshold voltage (VTH), subthreshold swing (SS), the Early voltage VEA and the intrinsic gain voltage (AV). The effects of strain techniques are also studied. The...
The experimental comparison between relaxed and strained Ge pFinFETs operating at room temperature is discussed. Although, the strain into the channel improves the drain current for wide transistors due to the boost of hole mobility, the gate stack engineering has to be further studied in order to solve the threshold voltage shift. The relaxed channel achieves a lower subthreshold swing compared to...
This paper presents an experimental comparison of the analog performance between a triple-gate FinFET fabricated on Bulk (BFF) and on Silicon-On-Insulator — SOI (SFF) substrates. This comparison was performed based on the drain current, subthreshold swing, transconductance, output conductance and finally the intrinsic voltage gain. For narrow fin width, the SFF presents better performance than BFF,...
In this work the pTFET is evaluated from analog application point of view, through a direct comparison with the well-known pFinFET performance. This evaluation is mainly focused on the intrinsic voltage gain and the unity gain frequency. Although the total capacitance of FinFETs showed to be worse than for pTFETs, the transconductance behavior plays the main role and results in a higher unity gain...
In this work the back bias influence on the analog performance of tunnel-FETs is evaluated experimentally for the first time. The analysis of the transconductance, output conductance and intrinsic voltage gain (Av) was performed by comparing the pTFET behavior with a well-known pFinFET that was fabricated using the same process flow. Numerical simulations were also performed in order to explain the...
A single transistor 1T-DRAM, also called Floating-Body RAM cell (FBRAM) makes use of the transistor floating body as a charge storage node. Nowadays, it has become of high interest because it overcomes the integration problems associated with the capacitor of the conventional 1T/1C DRAM. In order to improve the retention time and sense margin, the parasitic BJT (Gen2) programming shows the best performance...
The continuous reduction of the devices has driven the scientific community to explore alternative technologies that are compatible with CMOS technology, but with different operating principles. The Tunnel Field Effect Transistors (TFETs) are a new conception of devices that have been proposed as a promising option to replace conventional MOSFETs, since its physical structure allows a very steep subthreshold...
The stringent requirements imposed by the ITRS rely on the introduction of alternative and/or new gate concepts and the implementation of advanced processing modules and materials[1]. During the last decade, alternative gate concepts, with an evolution from planar single gate to double gate, multi-gate FET (MugFET) or FinFET, and gate-all-around (GAA) or nanowire concepts have been extensively studied...
MuGFET devices show good gate-to-channel control, reducing short channel effects and increased current drive [1] and their performance can be improved through implementation of mechanical stress in the silicon fin. In th is wor k we study t he stress distr ibution and transconductance behavior in unstrained and biaxially + uniaxially strained tri-gate SOI nMOSFETs with different fin dimensions through...
In this paper we explore, from DC measurements, the impact of gate length scaling on the main digital/analog parameters of Ultra-Thin Buried Oxide (UTBOX) Fully Depleted Silicon-on-Insulator (FDSOI) devices at different temperatures. Standard junction reference devices are compared with the extension-less ones where the latter present superior characteristics for smaller device lengths such as improved...
The stress profiles extracted showed that the variation in the silicon fin dimensions influence the stress levels and distributions along the silicon fin. From the analog performance view, these variations in the stress have influence on some electric parameters. The reduction of the total fin length showed no significant change in the parameters, although a reduction in the stress level was noticed,...
The impact of a 60 MeV proton irradiation on the drain induced barrier lowering is investigated for tri-gate FinFETs processed with and without the implementation of different biaxial or uniaxial strain engineering techniques. A contrasting behavior is observed for n- and pFinFETs, which may be associated with the radiation-induced charges in the buried oxide and the influence of the back channel...
FinFET devices are explicitly mentioned in the ITRS roadmap and have a good potential for scaling CMOS to 22 nm and below. Some physical characterization and reliability aspects of these devices are reviewed. Attention is given to transient floating body effects and low frequency noise, which may yield information on the materials' characteristics like carrier recombination lifetime or interface and...
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