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Sparse matrix vector multiplication (SpMxV) is a core operation in many engineering, scientific and financial applications. Due to the sparse nature of the underlying matrices, irregular memory access patterns and short row lengths often slow down the performance significantly. Past implementations of SpMxV have been reported to be run at 10% or less of the machine's peak capability. In this paper...
This paper presents a complete design of a reconfigurable architecture support system, called ACS (an addressless configuration support), which provides efficient access to non-contiguous reconfigurable locations in reconfigurable systems. ACS reduces the amount of partial reconfiguration information required by removing a large amount of addressing information and padding as found in Virtex-4 bitstreams...
The increase of operating frequency of microprocessors has begun to meet more obstacles. Performance of single-thread applications no longer benefits from running under a faster processor. As a result, the performance increase has to come from additional hardware support which makes use of the large number of transistors available. This paper presents a novel hardware support called distTree to speed...
The aim of this paper is to present a novel reconfigurable architecture support which provides efficient access to noncontiguous locations in an array-like structure, whether it be memories or configurable logic blocks (Claw) in reconfigurable systems. This distribution tree (distTree) architecture serves as a mean of address resolution so that no addressing information is required externally or explicitly...
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