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An efficient VLSI architecture of motion compensation of MPEG-4 is presented in this paper. Aiming at the memory accessing problem of the motion compensation, three special methods were adopted. First, a novel interpolation pixel buffering mechanism and the corresponding parallel interpolation structure were proposed to save the buffering storage consumption of the interpolation pixels distinctly...
Multiprocessor System-on-Chip is a promising solution for the high performance Embedded System. This paper is based on an independent research about Hierarchical NoC (Network-on-chip). By integrating 16 ARM cores in the FPGA board, we can bring out the four-channel fade-in and fade-out for real-time streaming media. We present two parallel models for our multiprocessor. One is fine-grained parallelization,...
Network on chip (NoC) has been proposed as new on-chip communication paradigm for the multi-core processing era. But the memory wall problem is a design bottleneck, especially in real-time applications. This paper proposes a high throughput memory data-path design that can guarantee real-time I/O throughput for an in-house developed multi-core system. The main contribution is as follows: Firstly,...
New tendencies envisage multiprocessor systems-on-chips (MPSoCs) as a promising solution for high performance embedded system. And the key challenge is how to improve the communication efficiency. Network on Chip (NoC) has been considered as a new paradigm in the next generation communication architecture for its scalability and power efficiency. A NoC prototype which consists of 8 ARM compatible...
The importance of the memory hierarchy has increased with advances in performance of processors in chip multi-processor (CMP) system. However, the research of on chip memory subsystem for multiprocessor has not been undertaken thoroughly. In this paper, we develop two distributed shared memory hierarchies based on distributed shared-bus and network-on-chip (NoC), and the performances of these prototype...
Aiming at the requirements of real-time ability and good observability of result-checking in IC functional verification, a method was proposed to generate monitors automatically. Based on the requirements of the design property to be monitored, a sub-set was defined from the Property Specification Language (PSL), so that the objects to be monitored can be formally described. Based on the formal descriptions,...
With the development of IC technology, the commutation architecture has become a major bottleneck in Multi-processor System on Chip (MPSoC) design, which imposes communication based design into computation based design. It must provide enough bandwidth as well as the latency requirement. Network on Chip (NoC) has been considered as a new paradigm for its extensibility and power efficiency. This paper...
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